R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 7/08/2024
Public
Document Table of Contents

2.3.2.3. PIO Design Example Testbench

The figure below shows the PIO design example simulation design hierarchy. The tests for the PIO design example are defined with the apps_type_hwtcl parameter set to 3. The tests run under this parameter value are defined in ebfm_cfg_rp_ep_rootport, find_mem_bar, and downstream_loop.

Figure 29. PIO Design Example Simulation Design Hierarchy
The testbench starts with link training and then accesses the configuration space of the IP for enumeration. A task called downstream_loop (defined in the Root Port PCIe BFM altpcietb_bfm_rp_gen5_x16.sv) then performs the PCIe link test. This test consists of the following steps:
  1. Issues a memory write command to write a single dword of data into the on-chip memory behind the Endpoint.
  2. Issues a memory read command to read back data from the on-chip memory.
  3. Compares the read data with the write data. If they match, the test counts this as a Pass.
  4. Repeats Steps 1, 2, and 3 for one iteration.

The first memory write takes place around 219 us. It is followed by a memory read on the Avalon® -ST RX interface of the R-Tile Hard IP for PCIe. The Completion TLP appears shortly after the memory read request on the Avalon® -ST TX interface.

Note: In the 2x8 design example, memory read and memory write transactions are simulated on Port 0 only.