R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 7/08/2024
Public
Document Table of Contents

2.5. Compiling the Design Example

  1. Navigate to <project_dir>/intel_rtile_pcie_ast_0_example_design/ and open pcie_ed.qpf.
  2. If you select a specific development kit when generating the design example, the VID-related settings are included in the .qsf file and you are not required to add them manually. Note that these settings are board-specific.
  3. On the Processing menu, select Start Compilation.