R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 7/08/2024
Public
Document Table of Contents

2.2.2. Generating the Performance Design Example for TL Bypass Mode

If you want to generate the Performance design example for the TL Bypass mode, perform the following steps to enable TL Bypass Performance:
  1. On the Top-Level Settings tab, set the PCIe Hard IP Mode parameter to Gen5 1x16, interface - 1024-bit.
  2. On the Port Mode tab, select Upstream.
  3. On the Example Designs tab, make the following selections:
    1. For Available Example Designs, select the Performance Design Example.
    2. For Example Design Files, turn on the Simulation and Synthesis option. If you do not need these simulation or synthesis files, leaving the corresponding option(s) turned off significantly reduces the example design generation time.
      Note: Simulation is not supported for the Performance design example for TL Bypass mode in this release. Only synthesis is needed.
    3. For Generated HDL Format, select Verilog.
    4. For Target Development Kit, select the appropriate development kit.
      Note: If you select None, the generated design example targets the device you specified in the Family, Device & Board Settings and Target Device parameters. If you intend to test the design in hardware, make the appropriate pin assignments in the .qsf file. You can also use the pin planner tool to make pin assignments.
      Note: If you select a development kit, the device on that board overwrites the device selected in the Quartus® Prime project if the devices are different.
      Note: For Currently Selected Example Design, select PERFORMANCE_DESIGN.