Visible to Intel only — GUID: ewa1413308516621
Ixiasoft
1. Introduction to Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide
2. Reviewing Your Kernel's report.html File
3. OpenCL Kernel Design Concepts
4. OpenCL Kernel Design Best Practices
5. Profiling Your Kernel to Identify Performance Bottlenecks
6. Strategies for Improving Single Work-Item Kernel Performance
7. Strategies for Improving NDRange Kernel Data Processing Efficiency
8. Strategies for Improving Memory Access Efficiency
9. Strategies for Optimizing FPGA Area Usage
10. Strategies for Optimizing Intel® Stratix® 10 OpenCL Designs
11. Strategies for Improving Performance in Your Host Application
12. Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide Archives
A. Document Revision History for the Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide
2.1. High-Level Design Report Layout
2.2. Reviewing the Summary Report
2.3. Viewing Throughput Bottlenecks in the Design
2.4. Using Views
2.5. Analyzing Throughput
2.6. Reviewing Area Information
2.7. Optimizing an OpenCL Design Example Based on Information in the HTML Report
2.8. Accessing HLD FPGA Reports in JSON Format
4.1. Transferring Data Via Intel® FPGA SDK for OpenCL™ Channels or OpenCL Pipes
4.2. Unrolling Loops
4.3. Optimizing Floating-Point Operations
4.4. Allocating Aligned Memory
4.5. Aligning a Struct with or without Padding
4.6. Maintaining Similar Structures for Vector Type Elements
4.7. Avoiding Pointer Aliasing
4.8. Avoid Expensive Functions
4.9. Avoiding Work-Item ID-Dependent Backward Branching
5.1. Best Practices for Profiling Your Kernel
5.2. Instrumenting the Kernel Pipeline with Performance Counters (-profile)
5.3. Obtaining Profiling Data During Runtime
5.4. Reducing Area Resource Use While Profiling
5.5. Temporal Performance Collection
5.6. Performance Data Types
5.7. Interpreting the Profiling Information
5.8. Profiler Analyses of Example OpenCL Design Scenarios
5.9. Intel® FPGA Dynamic Profiler for OpenCL™ Limitations
8.1. General Guidelines on Optimizing Memory Accesses
8.2. Optimize Global Memory Accesses
8.3. Performing Kernel Computations Using Constant, Local or Private Memory
8.4. Improving Kernel Performance by Banking the Local Memory
8.5. Optimizing Accesses to Local Memory by Controlling the Memory Replication Factor
8.6. Minimizing the Memory Dependencies for Loop Pipelining
8.7. Static Memory Coalescing
Visible to Intel only — GUID: ewa1413308516621
Ixiasoft
5.2. Instrumenting the Kernel Pipeline with Performance Counters (-profile)
To instrument the OpenCL kernel pipeline with performance counters, include the -profile=(all|autorun|enqueued) option of the aoc command when you compile your kernel.
Note: Instrumenting the Verilog code with performance counters increases hardware resource utilization (that is, increases FPGA area usage) and typically decreases performance.
To instrument the Verilog code in the <your_kernel_filename>.aocx file with performance counters, invoke the aoc -profile=(all|autorun|enqueued) <your_kernel_filename>.cl command, where:
- all argument instruments all kernels in the <your_kernel_filename>.cl file with performance counters. This is the default option if no argument is provided.
- autorun argument instruments only the autorun kernels with performance counters.
- enqueued argument instruments only the non-autorun kernels with performance counters.
Note:
- When profiling multiple, different kernels, do not use the same kernel names across different .aocx files. If the kernel names are the same, the profile data is wrong for these kernels.
- Regardless of the input to the clGetProfileDataDeviceIntelFPGA host library call, the Intel® FPGA dynamic profiler for OpenCL™ only profiles kernel types that you indicate during compilation.
- Instrumenting the OpenCL kernel pipeline with performance counters on all or enqueued kernels disables the use of hardware kernel invocation queue by the OpenCL runtime environment. This may result in different profile time.
CAUTION:
Profiling autorun kernels results in some hardware overhead for the counters. For large designs, the overhead can cause fMAX and design frequency degradation. It can also lead to designs that cannot fit on the chip if the Intel® FPGA dynamic profiler for OpenCL™ profiles every kernel.