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Ixiasoft
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Ixiasoft
10.6. Creating RTL Modules
For more information about Intel® Stratix® 10-specific RTL design best practices, refer to the Intel® Stratix® 10 High-Performance Design Handbook.
There are stall-free and stallable RTL modules. A stall-free RTL module is a fixed-latency module for which the offline compiler can optimize away stall logic. Refer to the Stall-Free RTL section in the Intel® FPGA SDK for OpenCL™ Pro Edition Programming Guide for more information.
A stallable RTL module has variable latency and relies on backpressured input and output interfaces to function correctly. Implementing stallable interfaces in Intel® Stratix® 10 designs consumes a lot of FPGA resources because of the handshake logic, which limits retiming. Using stallable interfaces in Intel® Stratix® 10 designs also disables the data path control optimization scheme.
Intel® strongly recommends that you use stall-free RTL modules because the offline compiler can incorporate them into your Intel® Stratix® 10 designs more effectively.