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1. Introduction to Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide
2. Reviewing Your Kernel's report.html File
3. OpenCL Kernel Design Concepts
4. OpenCL Kernel Design Best Practices
5. Profiling Your Kernel to Identify Performance Bottlenecks
6. Strategies for Improving Single Work-Item Kernel Performance
7. Strategies for Improving NDRange Kernel Data Processing Efficiency
8. Strategies for Improving Memory Access Efficiency
9. Strategies for Optimizing FPGA Area Usage
10. Strategies for Optimizing Intel® Stratix® 10 OpenCL Designs
11. Strategies for Improving Performance in Your Host Application
12. Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide Archives
A. Document Revision History for the Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide
2.1. High-Level Design Report Layout
2.2. Reviewing the Summary Report
2.3. Viewing Throughput Bottlenecks in the Design
2.4. Using Views
2.5. Analyzing Throughput
2.6. Reviewing Area Information
2.7. Optimizing an OpenCL Design Example Based on Information in the HTML Report
2.8. Accessing HLD FPGA Reports in JSON Format
4.1. Transferring Data Via Intel® FPGA SDK for OpenCL™ Channels or OpenCL Pipes
4.2. Unrolling Loops
4.3. Optimizing Floating-Point Operations
4.4. Allocating Aligned Memory
4.5. Aligning a Struct with or without Padding
4.6. Maintaining Similar Structures for Vector Type Elements
4.7. Avoiding Pointer Aliasing
4.8. Avoid Expensive Functions
4.9. Avoiding Work-Item ID-Dependent Backward Branching
5.1. Best Practices for Profiling Your Kernel
5.2. Instrumenting the Kernel Pipeline with Performance Counters (-profile)
5.3. Obtaining Profiling Data During Runtime
5.4. Reducing Area Resource Use While Profiling
5.5. Temporal Performance Collection
5.6. Performance Data Types
5.7. Interpreting the Profiling Information
5.8. Profiler Analyses of Example OpenCL Design Scenarios
5.9. Intel® FPGA Dynamic Profiler for OpenCL™ Limitations
8.1. General Guidelines on Optimizing Memory Accesses
8.2. Optimize Global Memory Accesses
8.3. Performing Kernel Computations Using Constant, Local or Private Memory
8.4. Improving Kernel Performance by Banking the Local Memory
8.5. Optimizing Accesses to Local Memory by Controlling the Memory Replication Factor
8.6. Minimizing the Memory Dependencies for Loop Pipelining
8.7. Static Memory Coalescing
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2.8. Accessing HLD FPGA Reports in JSON Format
In addition to the report.html file, the Intel® FPGA SDK for OpenCL™ also provides the HLD FPGA Report data in JSON files.
The JSON files containing the HLD FPGA Report report data are available in the <your_kernel_filename>/reports/lib/json directory. The directory provides the following .json files:
File | Description |
---|---|
area.json | Area Analysis of System |
block.json | Block View of System Viewer |
bottleneck.json | Bottleneck View of Loop Analysis Report |
gmv.json | Global Memory View of the System Viewer |
info.json | Summary of project name, compilation command, versions, and timestamps |
loops.json | Navigation tree of Loop Analysis report |
loops_attr.json | Loop Analysis report |
mav.json | System View of System Viewer |
new_lmv.json | Kernel Memory Viewer |
pipeline.json | Cluster View of System Viewer |
quartus.json | Quartus Prime compilation summary |
schedule.json | Schedule Viewer |
summary.json | Kernel compilation name mapping |
tree.json | Navigation tree of System Viewer |
warnings.json | Compilation warning messages |
Important: The structure of these JSON files might change from release to release without notice.
You can read the following .json files without a special parser:
- area.json
- area_src.json
- loops.json
- quartus.json
- summary.json
For example, if you want to identify all of the values and bottlenecks for the initiation interval (II) of a loop, you can find the information in the children section in the loops.json file, as shown below:
“name”:”<block name|Kernel: kernel name> # Find the loops which does not begin with “Kernel:” “data”:[<Yes|No>, <#|n/a>, <II|n/a>] # The data field corresponds to “Pipelined”, “II”, “Bottleneck”