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2.1. I/O Standards and Voltage Levels in Intel® Stratix® 10 Devices
2.2. I/O Element Structure in Intel® Stratix® 10 Devices
2.3. Programmable IOE Features in Intel® Stratix® 10 Devices
2.4. On-Chip I/O Termination in Intel® Stratix® 10 Devices
2.5. External I/O Termination for Intel® Stratix® 10 Devices
3.1. Guideline: VREF Sources and VREF Pins
3.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing
3.3. Guideline: Voltage-Referenced and Non-Voltage Referenced I/O Standards
3.4. Guideline: Do Not Drive I/O Pins During Power Sequencing
3.5. Guideline: Intel® Stratix® 10 I/O Buffer During Power Up, Configuration, and Power Down
3.6. Guideline: Maximum DC Current Restrictions
3.7. Guideline: Use Only One Voltage for All 3 V I/O Banks
3.8. Guideline: I/O Standards Limitation for Intel® Stratix® 10 TX 400
3.9. Guideline: I/O Standards Limitation for Intel® Stratix® 10 GX 400 and SX 400
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4.3.1. Timing Components
The GPIO IP timing components consist of three paths.
- I/O interface paths—from the FPGA to external receiving devices and from external transmitting devices to the FPGA.
- Core interface paths of data and clock—from the I/O to the core and from the core to I/O.
- Transfer paths—from half-rate to full-rate DDIO, and from full-rate to half-rate DDIO.
Note: The Timing Analyzer treats the path inside the DDIO_IN and DDIO_OUT blocks as black boxes.
Figure 31. Input Path Timing Components
Figure 32. Output Path Timing Components
Figure 33. Output Enable Path Timing Components