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2.1. I/O Standards and Voltage Levels in Intel® Stratix® 10 Devices
2.2. I/O Element Structure in Intel® Stratix® 10 Devices
2.3. Programmable IOE Features in Intel® Stratix® 10 Devices
2.4. On-Chip I/O Termination in Intel® Stratix® 10 Devices
2.5. External I/O Termination for Intel® Stratix® 10 Devices
3.1. Guideline: VREF Sources and VREF Pins
3.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing
3.3. Guideline: Voltage-Referenced and Non-Voltage Referenced I/O Standards
3.4. Guideline: Do Not Drive I/O Pins During Power Sequencing
3.5. Guideline: Intel® Stratix® 10 I/O Buffer During Power Up, Configuration, and Power Down
3.6. Guideline: Maximum DC Current Restrictions
3.7. Guideline: Use Only One Voltage for All 3 V I/O Banks
3.8. Guideline: I/O Standards Limitation for Intel® Stratix® 10 TX 400
3.9. Guideline: I/O Standards Limitation for Intel® Stratix® 10 GX 400 and SX 400
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4.6. IP Migration to the GPIO IP Core
The GPIO IP core can migrate your GPIO IPs from previous devices to work in Intel® Stratix® 10 designs.
Depending on the mode you use in your previous IP, the IP migration tool can automatically configure the new GPIO IP core based on settings in your previous IP. For unsupported modes, you can use the GPIO IP core parameter editor to manually configure the migrated IP core.