Intel® Stratix® 10 General Purpose I/O User Guide

Download PDF
ID 683518
Date 9/13/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 I/O Overview 2. Intel® Stratix® 10 I/O Architecture and Features 3. Intel® Stratix® 10 I/O Design Considerations 4. Intel® Stratix® 10 I/O Implementation Guides 5. GPIO Intel® FPGA IP Reference 6. Document Revision History for Intel® Stratix® 10 General Purpose I/O User Guide
1. Intel® Stratix® 10 I/O Overview x
1.1. Intel® Stratix® 10 I/O and Differential I/O Buffers 1.2. Intel® Stratix® 10 I/O Migration Support
2. Intel® Stratix® 10 I/O Architecture and Features x
2.1. I/O Standards and Voltage Levels in Intel® Stratix® 10 Devices 2.2. I/O Element Structure in Intel® Stratix® 10 Devices 2.3. Programmable IOE Features in Intel® Stratix® 10 Devices 2.4. On-Chip I/O Termination in Intel® Stratix® 10 Devices 2.5. External I/O Termination for Intel® Stratix® 10 Devices
2.1. I/O Standards and Voltage Levels in Intel® Stratix® 10 Devices x
2.1.1. Intel® Stratix® 10 I/O Standards Support 2.1.2. Intel® Stratix® 10 I/O Standards Voltage Support
2.2. I/O Element Structure in Intel® Stratix® 10 Devices x
2.2.1. I/O Bank Architecture in Intel® Stratix® 10 Devices 2.2.2. I/O Buffer and Registers in Intel® Stratix® 10 Devices
2.3. Programmable IOE Features in Intel® Stratix® 10 Devices x
2.3.1. Programmable Output Slew Rate Control 2.3.2. Programmable IOE Delay 2.3.3. Programmable Open-Drain Output 2.3.4. Programmable Bus Hold 2.3.5. Programmable Pull-Up Resistor 2.3.6. Programmable Pre-Emphasis 2.3.7. Programmable Differential Output Voltage 2.3.8. Programmable Current Strength
2.4. On-Chip I/O Termination in Intel® Stratix® 10 Devices x
2.4.1. RS OCT without Calibration in Intel® Stratix® 10 Devices 2.4.2. RS OCT with Calibration in Intel® Stratix® 10 Devices 2.4.3. RT OCT with Calibration in Intel® Stratix® 10 Devices 2.4.4. Dynamic OCT 2.4.5. Differential Input RD OCT 2.4.6. OCT Calibration Block in Intel® Stratix® 10 Devices
2.5. External I/O Termination for Intel® Stratix® 10 Devices x
2.5.1. Single-Ended I/O Termination 2.5.2. Differential I/O Termination for Intel® Stratix® 10 Devices
2.5.2. Differential I/O Termination for Intel® Stratix® 10 Devices x
2.5.2.1. Differential HSTL, SSTL, HSUL, and POD Termination 2.5.2.2. LVDS, RSDS, and Mini-LVDS Termination 2.5.2.3. LVPECL Termination
3. Intel® Stratix® 10 I/O Design Considerations x
3.1. Guideline: VREF Sources and VREF Pins 3.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing 3.3. Guideline: Voltage-Referenced and Non-Voltage Referenced I/O Standards 3.4. Guideline: Do Not Drive I/O Pins During Power Sequencing 3.5. Guideline: Intel® Stratix® 10 I/O Buffer During Power Up, Configuration, and Power Down 3.6. Guideline: Maximum DC Current Restrictions 3.7. Guideline: Use Only One Voltage for All 3 V I/O Banks 3.8. Guideline: I/O Standards Limitation for Intel® Stratix® 10 TX 400 3.9. Guideline: I/O Standards Limitation for Intel® Stratix® 10 GX 400 and SX 400
4. Intel® Stratix® 10 I/O Implementation Guides x
4.1. GPIO Intel® FPGA IP 4.2. Verifying Resource Utilization and Design Performance 4.3. GPIO Intel® FPGA IP Timing 4.4. GPIO Intel® FPGA IP Design Examples 4.5. Verifying Pin Migration Compatibility 4.6. IP Migration to the GPIO IP Core
4.1. GPIO Intel® FPGA IP x
4.1.1. Release Information for GPIO Intel® FPGA IP 4.1.2. GPIO Intel® FPGA IP Data Paths 4.1.3. Register Packing
4.1.2. GPIO Intel® FPGA IP Data Paths x
4.1.2.1. Input Path 4.1.2.2. Output and Output Enable Paths
4.3. GPIO Intel® FPGA IP Timing x
4.3.1. Timing Components 4.3.2. Delay Elements 4.3.3. Timing Analysis 4.3.4. Timing Closure Guidelines
4.3.3. Timing Analysis x
4.3.3.1. Single Data Rate Input Register 4.3.3.2. Full-Rate or Half-Rate DDIO Input Register 4.3.3.3. Single Data Rate Output Register 4.3.3.4. Full-Rate or Half-Rate DDIO Output Register
4.4. GPIO Intel® FPGA IP Design Examples x
4.4.1. GPIO Intel® FPGA IP Synthesizable Intel® Quartus® Prime Design Example 4.4.2. GPIO Intel® FPGA IP Simulation Design Example
4.6. IP Migration to the GPIO IP Core x
4.6.1. Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores 4.6.2. Guideline: Swap datain_h and datain_l Ports in Migrated IP
5. GPIO Intel® FPGA IP Reference x
5.1. GPIO Intel® FPGA IP Parameter Settings 5.2. GPIO Intel® FPGA IP Interface Signals
5.2. GPIO Intel® FPGA IP Interface Signals x
5.2.1. Shared Signals 5.2.2. Data Bit-Order for Data Interface 5.2.3. Data Interface Signals and Corresponding Clocks
1. Intel® Stratix® 10 I/O Overview
2. Intel® Stratix® 10 I/O Architecture and Features
3. Intel® Stratix® 10 I/O Design Considerations
4. Intel® Stratix® 10 I/O Implementation Guides
5. GPIO Intel® FPGA IP Reference
6. Document Revision History for Intel® Stratix® 10 General Purpose I/O User Guide

6. Document Revision History for Intel® Stratix® 10 General Purpose I/O User Guide

Document Version Intel® Quartus® Prime Version Changes
2023.09.13 23.2
  • Updated the IP migration guideline to specify that the GPIO IP drives datain_h on the falling edge and datain_l on the rising edge.
  • Updated links.
2022.09.29 22.3
  • Corrected the output clock name in the topic about the single data rate output register from sdr_out_clk to sdr_out_outclk.
  • In the guideline for VREF sources and VREF pins, clarified that the internal VREF is supported only for external memory interfaces.
  • Updated the GPIO IP version to 21.0.0.
2021.07.07 21.2
  • Added 2.5 V LVCMOS support for the open-drain output, bus-hold, and weak pull-up resistor features in the table listing the programmable IOE features I/O buffer types and I/O standards support.
  • Updated the diagram that shows the simplified view of the single-ended GPIO input path to update dout[0] to dout[3] and dout[3] to dout[0].
2021.03.29 21.1 Updated the GPIO IP version number to 20.0.0.
2021.03.12 20.4 Updated the IP migration guideline to specify that the GPIO IP drives datain_h on the rising edge and datain_l on the falling edge.
2020.11.13 20.3 Updated the figure showing the I/O bank structure to add the pin naming orientation.
2020.08.25 20.2 Updated the topic about the I/O and differential I/O buffers to remove differential I/O support from 3 V I/O bank and to improve clarity.
2020.07.14 20.2
  • Added Intel® Stratix® 10 GX 10M to the figure showing the migration capability across Intel® Stratix® 10 GX and SX product lines.
  • In the table listing the supported I/O standards voltage levels, updated the 3.3 V LVTTL/3.3 V LVCMOS row to support only 3.3 V VCCIO input, and the 3.0 V LVVTL/3.0 V LVCMOS row to support only 3.0 V VCCIO input.
  • Updated the figure showing the I/O bank structure:
    • Added I/O bank structure for Intel® Stratix® 10 GX 10M device.
    • For I/O banks figure of other Intel® Stratix® 10 devices:
      • Marked only bank 3A as SDM shared LVDS I/O
      • Marked HPS shared LVDS I/Os
      • Added 3 V I/O banks 7A, 7B, and 7C
  • Updated the topic about programmable IOE delay to improve clarity.
  • Removed the weak pull-up control feature in bank 3C of the HF35 package of Intel® Stratix® 10 GX 400 and SX 400 devices:
    • Updated the programmable IOE features topic.
    • Updated the I/O standards limitation guidelines for Intel® Stratix® 10 GX 400 and SX 400 devices.
  • Updated the available programmable current strength settings for 3.3 V I/O standards.
  • Added guideline topic about I/O buffer behavior during device power up, configuration, and power down.
2020.01.08 19.4
  • Updated the I/O migration topic to add and remove variants, product lines, packages, and migration paths.
  • Added 3.3 V I/Os for package HF35 of the Intel® Stratix® 10 GX 400 and SX 400 devices.
  • Added support for RS OCT without calibration for 3 V I/Os.
  • Updated the design guideline for I/O standards limitation in Intel® Stratix® 10 TX 400 devices to specify that you can use LVDS, mini-LVDS, or RSDS in banks 3A and 3D only as dedicated clock pins.
  • Added design guideline for I/O standards limitation in Intel® Stratix® 10 GX 400 and SX 400 devices.
  • Updated the programmable pre-emphasis diagram to remove the word "peak-peak".
  • Added related information link from the topic about the programmable pull-up resistor feature to the Configuration Flow Diagram topic in the Intel® Stratix® 10 Configuration User Guide. The linked topic provides more information about weak-pull up in configuration mode.
  • Updated the VREF sources and VREF pins design guideline to remove VCCIO from the guideline about connecting unused VREF pins.
2019.10.01 19.3

Corrected typographical error in the .qsf assignment codes in the topic about delay elements.

2019.09.30 19.3
  • Added the Intel® Stratix® 10 TX 400 device to the vertical migration table.
  • Added a guideline topic about using only one voltage for all 3 V I/O banks.
  • Added a guideline topic about not using LVDS, Mini-LVDS, or RSDS I/O standards in banks 3A or 3D of the Intel® Stratix® 10 TX 400 device.
2019.07.09 19.2

Updated the notes in the topics about the input path, and output and output enable paths to specify that the GPIO Intel® FPGA IP and OCT Intel® FPGA IP support OCT on single-directional input or output pins only.

2019.03.04 18.1 In the topics about the input path, and output and output enable paths:
  • Corrected the notes in the topics to specify that the GPIO Intel® FPGA IP does not support dynamic calibration of bidirectional pins.
  • Added links to the PHY Lite for Parallel Interfaces Intel® FPGA IP Core User Guide: Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX Devices for more information about applications that require dynamic calibration for bidirectional pins.
2019.01.23 18.1

Updated the Intel® Quartus® Prime version of the document.

2019.01.14 18.1
  • Removed statement that says that the programmable VOD value of "0" is not available for the LVDS I/O standard.
  • In the topic about dynamic OCT, added link to PHY Lite for Parallel Interfaces Intel® FPGA IP Core User Guide: Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX Devices for applications that require dynamic OCT for bidirectional pins.
2018.07.09 18.0
  • Added 24 mA and 20 mA current strength settings for the 3.0 V LVTTL I/O standard.
  • Added Differential SSTL-15 Class I and Class II, and Differential SSTL-18 Class I and Class II to the table that lists the programmable current strengths.
  • Added Differential SSTL-15 Class I and Class II to the tables that list the RS OCT with calibration and RS OCT without calibration.
  • Removed 50 Ω RT OCT for SSTL-15 and Differential SSTL-15 I/O standards.
  • Added a note about not pulling the output voltage higher than the Vi (DC) level in the topic about the programmable open drain output.
2018.05.10 18.0
  • Updated a footnote related to 3 V I/O to specify that the 3 V I/O is not supported in the E-Tile transceiver tiles.
  • Added a footnote to the I/O standards support table to specify that a transceiver tile's 3 V I/O bank is not available when the tile is powered down.
  • Removed DDR2 support.
  • Removed the topic about MultiVolt I/O interface and added the information to the topic about I/O standards voltage support.
  • Moved the I/O count tables and I/O banks location figures to the pin-out files.
  • Updated the figure titles in the topic about LVPECL termination to clarify that the figures refer to external termination. There is no OCT support for LVPECL I/O standard.
  • Clarified that to utilize the I/O registers when implementing DDR circuitry, use the GPIO Intel® FPGA IP in I/O Buffer and Registers in Intel® Arria® 10 Devices.
  • Clarified that all singled-ended I/O configured to 3 V I/O bank supports all programmable I/O elements except programmable pre-emphasis, RD on-chip termination (OCT), calibrated RS and RT OCT, and internal VREF generation.
  • Clarified that 3 V I/O bank supports single-ended and differential SSTL, HSTL, and HSUL I/O standards.
  • Specified that VREF pins are dedicated for voltage-reference signal-ended I/O standards in Guideline: VREF Sources and VREF Pins.
  • Clarified the type of I/O buffers available in Intel® Arria® 10 FPGA devices and Intel® Arria® 10 SoC devices in I/O Standards and Voltage Levels in Intel Stratix 10 Devices.
  • Changed logic-to-pin to logic to the output buffer in Programmable Open-Drain Output section.
  • Renamed the IP core from "Intel FPGA GPIO" to "GPIO Intel FPGA IP".
  • Corrected instances of "clk_fr" and "clk_hr" to "ck_fr" and "ck_hr".
  • Updated the GPIO IP core input path and output paths diagrams to show the actual IP core signal names.
  • Updated the table listing the reset interface signals to improve clarity.
Date Version Changes
November 2017 2017.11.06
  • Clarified that each 3 V I/O bank supports only two OEs for its eight single-ended I/Os.
  • Removed Intel® Stratix® 10 TX 4500 and TX 5500 devices.
  • Added package SF48 to Intel® Stratix® 10 TX 1650 and TX 2100 devices.
  • Added Intel® Stratix® 10 MX devices.
  • Specified that 3 V I/Os are not available for Intel® Stratix® 10 devices with E-Tile transceiver variants.
  • Updated descriptions of the table that lists the GPIO buffers and LVDS channels in Intel® Stratix® 10 GX devices to specify that the LVDS channels counts include dedicated clock pins.
  • Removed the HF50 package from all Intel® Stratix® 10 devices.
  • Restructured the topics and tables that list the I/O banks locations and pin counts.
  • Added support for 2.5 V LVCMOS I/O standard.
  • Added 3 V I/O bank support for the 1.8 V LVCMOS, 1.5 V LVCMOS, and 1.2 V LVCMOS I/O standards.
  • Removed all instances of "DDR3U". Intel validates and support only IPs for memory interfaces listed in Performance Support Summary, Intel® Stratix® 10 External Memory Interfaces User Guide.
  • Added a note to specify that to use the 1.2 V, 1.5 V, 1.8 V, and 2.5 V I/O standards on the 3 V I/O bank, you need to set the USE_AS_3V_GPIO assignment.
  • Updated the tables that lists the programmable IOE features supported by the I/O buffer types and I/O standards.
  • Removed the table that lists the I/O standards and current strengths that support programmable slew rate control.
  • Added information about the default slew rate setting.
  • Updated the topic about programmable IOE delay to remove the input and output delay information. The I/O delay numbers are pending characterization.
  • Added information about the default predefined current strength if you do not specifically assign a current strength in the Intel® Quartus® Prime software.
  • Updated the table listing the programmable current strength settings.
    • Added current strength settings for these I/O standards:
      • 2.5 V LVCMOS
      • SSTL-135 and Differential SSTL-135
      • SSTL-125 and Differential SSTL-125
      • SSTL-12 and Differential SSTL-12 Class I
      • POD12 and Differential POD12
      • Differential 1.8 V HSTL Class I and Class II
      • Differential 1.5 V HSTL Class I and Class II
      • Differential 1.2 V HSTL Class I
    • Removed 6 mA, 4 mA, and 2 mA HPS current strength settings for the 1.8 V LVCMOS I/O standard
    • Removed all HPS current strength settings except for the 1.8 V LVCMOS I/O standard
    • Removed 12 mA and 10 mA current strength settings from the following I/O standards:
      • 1.2 V LVCMOS
      • SSTL-18 Class I
      • SSTL-15 Class I
      • 1.2 V HSTL Class I
    • Removed 16 mA current strength settings from the SSTL-18 Class II and SSTL-15 Class II I/O standards
    • Updated the current strength setting from 16 mA to 14 mA for the 1.8 V HSTL Class II and 1.5 V HSTL Class II I/O standards
    • Removed programmable current strength for the 1.2 V HSTL Class II I/O standard
  • Removed OCT support for 3 V I/O.
  • Updated the tables listing the RS and RT OCT support to update I/O standards and available OCT settings.
  • Updated the tables listing the external termination schemes to add 2.5 V LVCMOS.
  • Updated the signal names in figures to match the signal names in the Intel FPGA GPIO IP core.
  • Added the output path waveform.
  • Renamed "Altera GPIO IP core" to "Intel FPGA GPIO IP core".
  • Clarified that the ASET and ACLR signals are active high.
September 2017 2017.09.04
  • Added 8 mA to SSTL-2 Class II, SSTL-18 Class II, and SSTL-15 Class II, and removed 12 mA from SSTL-18 Class II in the list of current strength settings that support programmable output slew rate control.
  • Added 8 mA current strength settings to SSTL-18 Class II and SSTL-15 Class II.
  • Added these I/O standards to the table listing the selectable I/O standards for RS OCT without calibration:
    • Differential SSTL-15
    • Differential SSTL-135
    • Differential SSTL-125
    • Differential SSTL-12
    • Differential HSUL-12
  • Added 16 mA current strength setting to 1.8 V LVCMOS I/O standard.
  • Added 12 mA and 10 mA current strength settings to 1.2 V LVCMOS I/O standard.
  • Removed 25 Ω and 50 Ω RS OCT settings from Differential SSTL-15 in the table that lists the selectable I/O standards for RS OCT with calibration.
  • Updated the table listing the Altera GPIO buffer parameters to specify the conditions for the Use bus-hold circuitry parameter option.
February 2017 2017.02.13
  • Removed the SF48 package from the Intel® Stratix® 10 TX 1650 and TX 2100 devices.
  • Updated topics to clarify that the 3 V I/O banks do not have I/O registers and DDIOs, and do not support all features of the Altera GPIO IP core.
December 2016 2016.12.05 Corrected the number of I/Os in I/O bank 3L for the HF55 package of the GX 4500 and SX 5500 devices.
October 2016 2016.10.31

Initial release.

Level Two Title