Visible to Intel only — GUID: glk1602633525744
Ixiasoft
Visible to Intel only — GUID: glk1602633525744
Ixiasoft
4.4.4. Deskew Signals
In PIPE Direct mode, the R-Tile Avalon Streaming Intel FPGA IP for PCI Express removes any lane-to-lane skew introduced while crossing the EMIB. A dedicated deskew marker is used for detecting and compensating for any multi-lane skew introduced by EMIB. The deskew logic can account for a maximum of up to 3 cycles of parallel skew. After a cold/warm/hot reset or CvP update, the deskew process will start.
The user application logic needs to send a deskew marker every 16 clock cycles for the purpose of deskewing the data on the EMIB channels. The R-Tile Avalon Streaming Intel FPGA IP for PCI Express runs the deskew process every time it receives the deskew marker.
PIPE Direct Tx Deskew Bundle | Octet 1 | Octet 0 | ||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Lane 15 | Lane 14 | Lane 13 | Lane 12 | Lane 11 | Lane 10 | Lane 9 | Lane 8 | Lane 7 | Lane 6 | Lane 5 | Lane 4 | Lane 3 | Lane 2 | Lane 1 | Lane 0 | |
1X16 | Octet1_Dsk_0 | Octet0_Dsk_0 | ||||||||||||||
2X8 | Octet1_Dsk_0 | Octet0_Dsk_0 | ||||||||||||||
4X4 | Octet1_Dsk_2 | Octet1_Dsk_0 | Octet0_Dsk_2 | Octet0_Dsk_0 | ||||||||||||
8X2 | Octet1_Dsk_3 | Octet1_Dsk_2 | Octet1_Dsk_1 | Octet1_Dsk_0 | Octet0_Dsk_3 | Octet0_Dsk_2 | Octet0_Dsk_1 | Octet0_Dsk_0 | ||||||||
16X1 | No Tx Deskew | |||||||||||||||
2X4; 1X8 | Octet1_Dsk_2 | Octet1_Dsk_0 | Octet0_Dsk_0 | |||||||||||||
4X2; 1X8 | Octet1_Dsk_3 | Octet1_Dsk_2 | Octet1_Dsk_1 | Octet1_Dsk_0 | Octet0_Dsk_0 | |||||||||||
8X1; 1X8 | No Tx Deskew | Octet0_Dsk_0 | ||||||||||||||
1X8; 2X4 | Octet1_Dsk_0 | Octet0_Dsk_2 | Octet0_Dsk_0 | |||||||||||||
4X2; 2X4 | Octet1_Dsk_3 | Octet1_Dsk_2 | Octet1_Dsk_1 | Octet1_Dsk_0 | Octet0_Dsk_2 | Octet0_Dsk_0 | ||||||||||
8X1; 2X4 | No Tx Deskew | Octet0_Dsk_0 | Octet0_Dsk_0 | |||||||||||||
1X8; 4X2 | Octet1_Dsk_0 | Octet0_Dsk_3 | Octet0_Dsk_2 | Octet0_Dsk_1 | Octet0_Dsk_0 | |||||||||||
2X4; 4X2 | Octet1_Dsk_2 | Octet1_Dsk_0 | Octet0_Dsk_3 | Octet0_Dsk_2 | Octet0_Dsk_1 | Octet0_Dsk_0 | ||||||||||
8X1; 4X2 | No Tx Deskew | Octet0_Dsk_3 | Octet0_Dsk_2 | Octet0_Dsk_1 | Octet0_Dsk_0 | |||||||||||
1X8; 8X1 | Octet1_Dsk_0 | No Tx Deskew | ||||||||||||||
2X4; 8X1 | Octet1_Dsk_2 | Octet1_Dsk_0 | No Tx Deskew | |||||||||||||
4X2; 8X1 | Octet1_Dsk_3 | Octet1_Dsk_2 | Octet1_Dsk_1 | Octet1_Dsk_0 | No Tx Deskew |