R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/06/2024
Public
Document Table of Contents

8. Document Revision History for the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.12.06 24.3 11.4.0 Fixed the configuration descriptions in Lane Margining.
2024.10.07 24.3 11.4.0
  • Updated the table of supported features in SR-IOV Supported Features List.
  • Updated the signal names in VF Error Flag Interface (for x16/x8 Cores Only).
  • Updated the signal names and timing diagram in PIPE Direct Reset Sequence.
  • Updated the timing diagram in PIPE Direct Speed Change.
2024.07.08 24.2 11.3.0
  • Added an example of BDF translation to the Avalon Streaming TX Interface section.
  • Fixed the directions of some signals in the PIPE Direct Reset Entry Sequence diagram under the PIPE Direct Reset Sequence section.
2024.04.10 24.1 11.2.0
  • Updated values in the Preset Mappings section.
  • Updated the timing diagram and text in the PIPE Direct Reset Sequence section.
  • Updated the timing diagram and text in the PIPE Direct Speed Change section.
  • Updated TLP Prefix, Header and Data when PCIe Header Format Checkbox is Disabled in the TLP Header and Data Alignment for the Avalon streaming RX and TX Interfaces section.
2023.12.04 23.4 11.1.0
  • Updated the description in the REFCLK and PERST Guidelines When Using Independent PERST Pins section.
  • Updated the refclk0, refclk1, refclk2 description in the Clocks section.
  • Added a description of the behavior of the pX_rx_stN_dvalid_o signal to the Application Logic Guidelines for the Avalon Streaming RX Interface section.
  • Updated the signal descriptions in the Power Management Interface section.
  • Updated the description in the Margin Masks Overview section.
2023.10.02 23.3 11.0.0
  • Updated the list of devices or OPNs supported for various features throughout the document.
  • Updated the screenshots in the Debug Toolkit section.
  • Updated some section headings in the Appendix Packets Forwarded to the User Application in TL Bypass Mode.
2023.06.26 23.2 10.0.0
  • Updated the Clocking section to include connection requirements for the input clocks refclk0, refclk1, and refclk2 for different Configuration Modes and different values of the Enable Independent Perst Pins parameter.
  • Added the Independent Perst Pins sub-section to the Reset section.
  • Added the requirement of using the Hard IP Reconfiguration Interface to access TL Bypass registers to the Register Settings for the TL Bypass Mode section.
  • Added some implementation considerations to the Precision Time Measurement (PTM) Interface (Endpoint Only) section.
  • Added the Enable Debug Toolkit, Enable Warm Perst, Enable Independent GPIO Perst, and Enable Independent Perst Pins parameters to the Top-Level Settings section. Updated corresponding screenshots of the IP Parameter Editor.
  • Updated IP Parameter Editor screenshots in the Core Parameters section.
2023.04.03 23.1 9.0.0
  • Updated product family name to "Agilex 7".
  • Updated all references to OPN numbers to differentiate between AGI OPNs and AGM OPNs.
  • Removed the section Bias Temperature Instability (BTI) Protection Mode.
  • Changed the section PMA/PCS to PMA since the PCS responsibilities are implemented by the MAC layer. Also changed all references to PCS to MAC, and some instances of PHY to PMA.
  • Updated the description of the pX_tx_st_ready_o signal in the Avalon Streaming TX Interface section.
  • Updated the guidelines in the Application Logic Guidelines for the Avalon Streaming TX Interface section.
  • Added example cases to the Avalon Streaming TX Interface pX_tx_st_ready_o Behavior section.
  • Added a Note on temperature monitoring to the Hard IP Reconfiguration Interface section.
  • Added a Note on temperature monitoring to the Overview section under the Debug Toolkit section.
  • Added a Note about the PHY Reconfiguration interface being automatically enabled to the Enabling the R-Tile Debug Toolkit section.
  • Added a Note about the availability of the Channel Parameters tab to the Channel Parameters section.
2022.12.19 22.4 8.0.0
  • Added guidelines for the Application logic to the Avalon Streaming RX Interface and Avalon Streaming TX Interface sections.
  • Moved the Enable the PHY Reconfiguration Interface from the Top-Level Settings section to the Avalon Parameters section to match the 22.4 IP Parameter Editor.
  • Updated screenshots in the Core Parameters section to match the 22.4 IP Parameter Editor.
  • Added the Link Inspector and the Channel Parameters sections.
2022.10.07 22.3 7.0.0 Updated the links to the configuration space register maps in the Configuration Space Registers section.
2022.09.26 22.3 7.0.0
  • Updated the information in the table Agilex Recommended FPGA Fabric Speed Grades for All Avalon Streaming Widths and Frequencies.
  • Added guidelines that the Application logic must follow to the Avalon Streaming RX Interface section.
  • Added guidelines that the Application logic must follow to the Avalon Streaming TX Interface section.
  • Updated the Troubleshooting/Debugging chapter to:
    • Add the information regarding hardware debugging, specifically how to debug link training issues, device enumeration issues, and performance and data transfer issues.
    • Add the list of top-level signals that can be monitored via the Signal Tap Logic Analyzer.
    • Add the list of interfaces that can be used for debug activities.
2022.06.20 22.2 6.0.0
  • Updated the Debug Toolkit section to document the additional capabilities for users to verify in hardware the status of the R-Tile Avalon® Streaming Intel FPGA IP for PCI Express.
  • Documented the new ports pX_cold_perst_n_i, pX_warm_perst_n_i, and pX_ip_rst_n_o.
  • Updated the Independent PERST section with new timing diagrams showing the behaviors of the pX_cold_perst_n_i and pX_warm_perst_n_i signals.
  • Updated the Hard IP Reconfiguration Interface section with a new timing diagram showing the behavior of the signals on this interface while doing a read of the configuration space registers.

2022.03.28 22.1 5.0.0
  • Removed Questa* FPGA Edition from the list of supported simulators in the Features section.
  • Updated the FPGA fabric speed grades table in the Performance and Resource Utilization section.
  • Updated the application clock frequencies table in the Clocking section.
  • Updated the list of PCI Express Capability Structure registers that need to be implemented in the Application logic in the Hard IP Reconfiguration Interface.
  • Updated the tables in the Completion Buffer Size section.
  • Added the subsections D3Hot Exit Initiated by Host, D3Hot Exit Initiated by EP, D3Cold Entry and D3Cold Exit to the Power Management Interface section.
  • Modified the list of steps given in the PIPE Direct Reset Sequence section.
  • Modified the description given in the PIPE Direct Speed Change section.
2021.12.13 21.4 4.0.0
  • Added the new section BTI Protection Mode.
  • Updated the Completion Buffer Size section to show the correct buffer sizes. Also added examples showing the amount of Completion buffer entries consumed for Memory Read requests. Finally, added a suggested flow for the Application logic to track the completion buffer entries and based on this, schedule Non-Posted (NP) requests to the R-Tile Avalon® Streaming Intel FPGA IP for PCI Express.
  • Updated the text descriptions and timing waveforms for the Avalon Streaming RX Interface and the Avalon Streaming TX Interface to show how the user application logic can properly use these interfaces.
  • Updated the signal descriptions and timing waveforms for the Deskew Channel section to show how the user application logic can properly use this interface.
2021.10.06 21.3 3.0.0 Removed the section ECRC due to missing information on the register offsets for the ECRC or LCRC counters.
2021.10.04 21.3 3.0.0
  • Updated the block diagrams in the PCI Express Mode and PIPE Direct Mode sections to match the interface signals on the 21.3 block symbol for the R-Tile Avalon® Streaming Intel FPGA IP for PCI Express.
  • Added a Note to the Avalon Streaming TX Interface section stating that for this interface, the SOP can only be sent on segments 0 and 2.
  • Added the Root Port Enumeration Appendix chapter.
2021.07.12 21.2 2.0.0 Initial release.