R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 7/08/2024
Public
Document Table of Contents

2.3.3.1. Preset Mappings

The R-Tile Avalon-ST FPGA IP when configured in PIPE Direct mode does not support querying the FS/LS/Preset/Coefficient values. Refer to the preset mappings below.

For the OPNs AGIx027R29AxxxxR0, AGIx027R29AxxxxR1:

Preset Preshoot (dB) De-emphasis (dB) C-1 (Pre) C0 (Main) C+1 (Post)
P0 0 -6 0 36 12
P1 0 -3.5 0 40 8
P2 0 -4.4 0 38 10
P3 0 -2.5 0 42 6
P4 0 0 0 48 0
P5 1.5 0 5 43 0
P6 2.5 0 6 42 0
P7 3.5 -6 4 34 10
P8 3.5 -3.5 6 36 6
P9 3.5 0 8 40 0

For Production devices or Engineering Samples with the following OPNs AGIx027R29AxxxxR2, AGIx027R29AxxxxR3, AGIx027R29BxxxxR3, AGIx023R18AxxxxR0, AGIx041R29DxxxxR0, AGIx041R29DxxxxR1, AGMx039R47AxxR0:

Preset Preshoot (dB) De-emphasis (dB) C-1 (Pre) C0 (Main) C+1 (Post)
P0 0 -6 0 36 12
P1 0 -3.5 0 40 8
P2 0 -4.4 0 38 10
P3 0 -2.5 0 42 6
P4 0 0 0 48 0
P5 1.5 0 5 43 0
P6 2.5 0 6 42 0
P7 3.5 -6 6 34 8
P8 3.5 -3.5 6 36 6
P9 3.5 0 8 40 0
In addition, EQ feedback direction is not supported. Only the Figure of Merit (FOM) must be implemented. Intel recommends transmitting the following preset values to the R-Tile Avalon-ST IP in PIPE Direct mode in order to recover data successfully.
  • For the OPNs AGIx027R29AxxxxR0, AGIx027R29AxxxxR1:
    • For Gen3/Gen4/Gen5: FS = 48, LF = 16
    • For Gen3/Gen5: {c-1, c0, c+1 = preset} = {8/40/0 = P9}
    • For Gen4: {c-1, c0, c+1 = preset} = {0/42/6 = P3}
  • For Production devices or Engineering Samples with the following OPNs AGIx027R29AxxxxR2, AGIx027R29AxxxxR3, AGIx027R29BxxxxR3, AGIx023R18AxxxxR0, AGIx041R29DxxxxR0, AGIx041R29DxxxxR1, AGMx039R47AxxR0:
    • For Gen3/Gen4/Gen5: FS = 48, LF = 16
    • For Gen5:

      {c-1, c0, c+1 = preset} = {6/36/6 = P8}

      {c-1, c0, c+1 = preset} = {8/40/0 = P9}

    • For Gen4:

      {c-1, c0, c+1 = preset} = {0/42/6 = P3}

      {c-1, c0, c+1 = preset} = {6/34/8 = P7}

    • For Gen3:

      {c-1, c0, c+1 = preset} = {0/48/0 = P4}

For additional details on OPN decoding, refer to the Available Options section of the Agilex™ 7 FPGAs and SoCs Device Overview.