R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 7/08/2024
Public
Document Table of Contents

1.7. IP Core Support Levels

The following table shows the support levels of the R-Tile Avalon® streaming Intel FPGA IP for PCI Express* IP core in Agilex™ 7 devices.

Table 9.  R-Tile Avalon streaming Intel FPGA IP for PCIe Support Matrix for Agilex™ 7 DevicesSupport level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support
EP RP BP UP/DN
16-channel PIPE Direct N/A N/A N/A
Gen5 x16 1024-bit SCTH SCTH SCTH
Gen4 x16 1024-bit SCTH SCTH SCTH
Gen3 x16 1024-bit SCTH SCTH SCTH
Gen4 x16 512-bit 4 SCTH SCTH SCTH
Gen3 x16 512-bit 4 SCTH SCTH SCTH
Gen5 x8/x8 512-bit SCTH SCTH SCTH
Gen4 x8/x8 512-bit SCTH SCTH SCTH
Gen3 x8/x8 512-bit SCTH SCTH SCTH
Gen4 x8/x8 256-bit 4 SCTH SCTH SCTH
Gen3 x8/x8 256-bit 4 SCTH SCTH SCTH
Gen5 x4/x4/x4/x4 256-bit SCTH SCTH SCTH
Gen4 x4/x4/x4/x4 256-bit SCTH SCTH SCTH
Gen3 x4/x4/x4/x4 256-bit SCTH SCTH SCTH
Gen4 x4/x4/x4/x4 128-bit 4 SCTH SCTH SCTH
Gen3 x4/x4/x4/x4 128-bit 4 SCTH SCTH SCTH
4 These configurations are only available in Production devices or Engineering Samples with the following OPNs: AGIx027R29AxxxxR2, AGIx027R29AxxxxR3, AGIx027R29BxxxxR3, AGIx023R18AxxxxR0, AGIx041R29DxxxxR0, AGIx041R29DxxxxR1, AGMx039R47AxxR0. For more details on OPN decoding, refer to the Available Options section of the Agilex™ 7 FPGAs and SoCs Device Overview.