R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 7/08/2024
Public
Document Table of Contents

4.3.12. Function-Level Reset (FLR) Interface (Endpoint Only)

FLR allows specific physical/virtual functions to be reset without affecting other physical/virtual functions or the link they share. This interface is only present in EP mode (for x16/x8 configurations).

Note: Only Ports 0 and 1 support FLR.
Table 78.  Function-Level Reset (FLR) Interface Signals
Signal Name Direction Description EP/RP/BP Clock Domain
pX_flr_rcvd_pf_o[7:0] where

X = 0, 1, 2, 3 (IP core number)

Output This is a pulse-based signal to indicate the start of an FLR. The Application Layer must perform actions necessary to clear any pending transactions associated with the function being reset. The Application Layer must also assert pX_flr_completed_pf_num_i[2:0] to indicate it has completed the FLR actions and is ready to reenable the PF. EP slow_clk
pX_flr_rcvd_vf_o where

X = 0, 1, 2, 3 (IP core number)

Output

A one-cycle pulse on this signal indicates that an FLR was received from the host targeting a VF.

EP slow_clk
pX_flr_rcvd_pf_num_o[2:0] where

X = 0, 1, 2, 3 (IP core number)

Output Parent PF number of the VF undergoing FLR. EP slow_clk
pX_flr_rcvd_vf_num_o[10:0] where

X = 0, 1, 2, 3 (IP core number)

Output VF number offset of the VF undergoing FLR. EP slow_clk
pX_flr_completed_pf_i[7:0] where

X = 0, 1, 2, 3 (IP core number)

Input

One bit per PF. A one-cycle pulse on any bit indicates that the application has completed the FLR sequence for the corresponding PF and is ready to be enabled.

EP slow_clk
pX_flr_completed_vf_i where

X = 0, 1, 2, 3 (IP core number)

Input A one-cycle pulse from the application reenables a VF. EP slow_clk
pX_flr_completed_pf_num_i[2:0] where

X = 0, 1, 2, 3 (IP core number)

Input Parent PF number of the VF to re-enable. EP slow_clk
pX_flr_completed_vf_num_i[10:0] where

X = 0, 1, 2, 3 (IP core number)

Input VF number offset of the VF to re-enable. EP slow_clk
pX_flr_completed_ready_o where

X = 0, 1, 2, 3 (IP core number)

Output

Value 0 indicates the previous message is pending. The new FLR completed should be held if pX_flr_completed_ready_o = 0.

EP slow_clk