R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 7/08/2024
Public
Document Table of Contents

5.2. Core Parameters

Depending on which Hard IP Mode you choose in the Top-Level Settings tab, you will see different tabs for setting the core parameters.

If you choose a 1x16 mode (Gen3, Gen4 or Gen5), only the PCIe0 Settings tab will appear.

Figure 50. Intel R-Tile Avalon® Streaming Top-Level IP Parameter Editor for PCIe Gen5 1x16 Mode

If you choose a 2x8 mode (Gen3, Gen4 or Gen5), only the PCIe0 Settings and PCIe1 Settings tabs will appear.

Figure 51. Intel R-Tile Avalon® Streaming Top-Level IP Parameter Editor for PCIe Gen5 2x8 Mode
Figure 52. Intel R-Tile Avalon® Streaming Top-Level IP Parameter Editor for PCIe Gen5 2x8 Mode with Support of Independent Perst Pins
Note: For a list of devices that support the Enable Independent Perst pins option, refer to Reset.

If you choose a 4x4 mode (Gen3, Gen4 or Gen5), the PCIe0 Settings, PCIe1 Settings, PCIe2 Settings and PCIe3 Settings tabs will appear.

Figure 53. Intel R-Tile Avalon® Streaming Top-Level IP Parameter Editor for PCIe Gen5 4x4 Mode