R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 7/08/2024
Public
Document Table of Contents

4.3.1.4.1. Application Logic Guidelines for the Avalon Streaming TX Interface

The following guidelines must be considered by the Application logic:
  • Application logic must adhere to the requirements for the pX_tx_st_ready_o signal behavior as outlined in Avalon Streaming TX Interface pX_tx_st_ready_o Behavior.
  • Transmission of a TLP must be uninterrupted when pX_tx_st_ready_o is asserted. The application must not deassert pX_tx_stN_valid_i between pX_tx_stN_sop_i and pX_tx_stN_eop_i unless there is backpressure from the R-Tile PCIe IP core indicated by the deassertion of pX_tx_st_ready_o.
    Note: Failing to meet this guideline may cause the transmission of a TLP with an invalid LCRC.
  • For the Configuration Mode 0 (1x16) in double-width mode, the start of a TLP (pX_tx_stN_sop_i) can only happen in segment 0 (st0) or segment 2 (st2) (i.e. a given TLP cannot start on segment 1 or segment 3).
  • For Configuration Mode 0 (1x16) in double-width mode, the header for segment 2 (st2_hdr) is allowed depending on the utilization for segment 0 and segment 1. Refer to the table below for the allowed conditions. Note that the table does not include all the signals for the Avalon Streaming TX interface. It only shows the relevant signals to highlight the valid cases where a TLP can be started on segment 2.

    Table 59.  Possible Combinations for the pX_tx_st2_sop_i in Configuration Mode 0 (1x16) Double-width Mode
    pX_tx_st0_sop_i pX_tx_st0_eop_i pX_tx_st0_hvalid_i pX_tx_st0_dvalid_i pX_tx_st1_sop_i pX_tx_st1_eop_i pX_tx_st1_hvalid_i pX_tx_st1_dvalid_i pX_tx_st2_sop_i pX_tx_st2_hvalid_i pX_tx_st2_dvalid_i
    1'b1 1'b1 1'b1 1'b1 1'b0 1'b0 1'b0 1'b0 1'b1 1'b1 1'b1
    1'b1 1'b0 1'b1 1'b1 1'b0 1'b1 1'b0 1'b1 1'b1 1'b1 1'b1
    1'b0 1'b1 1'b0 1'b1 1'b0 1'b0 1'b0 1'b0 1'b1 1'b1 1'b1
    1'b0 1'b0 1'b0 1'b1 1'b0 1'b1 1'b0 1'b1 1'b1 1'b1 1'b1
  • For Configuration Mode 1 (2x8) and Configuration Mode 2 (4x4) in double-width mode, the header for segment 1 (st1_hdr) is allowed depending on the utilization for segment 0. Refer to the table below for the allowed conditions. Note that the table does not include all the signals for the Avalon Streaming TX interface. It only shows the relevant signals to highlight the valid cases where a TLP can be started on segment 1.
    Table 60.  Possible Combinations for the pX_tx_st1_sop_i in Configuration Mode 1 (2x8) and Configuration Mode 2 (4x4), Both in Double-width Mode
    pX_tx_st0_sop_i pX_tx_st0_eop_i pX_tx_st0_hvalid_i pX_tx_st0_dvalid_i pX_tx_st1_sop_i pX_tx_st1_hvalid_i pX_tx_st1_dvalid_i
    1'b1 1'b1 1'b1 1'b1 1'b1 1'b1 1'b1
    1'b0 1'b1 1'b0 1'b1 1'b1 1'b1 1'b1
  • For a single TLP spanning across multiple segments, the application logic needs to send the TLP in the order of the segment index (segment st0 → st1 → st2 → st3 → st0).
  • If the TLP length of the TLP being transmitted is greater than the segment size, the segment used to assert the pX_tx_stN_eop_i signal is dictated by the TLP length.
  • If the TLP length being transmitted is less than the segment size (255 bits), the corresponding pX_tx_stN_eop_i signal needs to happen in the same segment where pX_tx_stN_sop_i is being asserted.
  • The maximum number of clock cycles allowed between the deassertion of pX_tx_st_ready_o and pX_tx_stN_valid_i is 16 coreclkout_hip cycles.
  • For Configuration Mode 0 (1x16) in single-width mode, the start of a TLP is allowed in one segment per clock cycle (i.e. st0_hdr/st0_data or st1_hdr/st1_data). In addition, If segment 1 is used, st0_data must be used by the previous TLP.