R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 7/08/2024
Public
Document Table of Contents

1.3.1. Multifunction and Virtualization Features

The R-Tile Avalon® streaming Intel FPGA IP for PCI Express* supports the following multifunction and virtualization features:
  • SR-IOV support (Port 0 and Port 1 only).
    Note: Ports 0 and 1 can support 8 PFs and 2K VFs. Ports 2 and 3 do not support SR-IOV, and only support 1 PF.
  • Access Control Service (ACS) capability.
    Note:
    ACS support for Ports 2 and 3 is only available in Production devices or Engineering Samples with the following OPNs:
    • AGIx027R29AxxxxR2
    • AGIx027R29AxxxxR3
    • AGIx027R29BxxxxR3
    • AGIx023R18AxxxxR0
    • AGIx041R29DxxxxR0
    • AGIx041R29DxxxxR1
    • AGMx039R47AxxR0
    For additional details on OPN decoding, refer to the Available Options section of the Agilex™ 7 FPGAs and SoCs Device Overview.
  • Alternative Routing-ID Interpretation (ARI).
  • Function Level Reset (FLR).
    Note: Only Ports 0 and 1 support FLR.
  • TLP Processing Hint (TPH).
    Note: TPH supports the "No Steering Tag (ST)" mode only.
  • Address Translation Services (ATS).
  • Process Address Space ID (PasID).
    Note: Scalable IO and Shared Virtual Memory (SVM) may be available in a future Quartus® Prime release.
  • Configuration Intercept Interface (CII).
    Note: CVP is not available when CII is enabled.
  • Soft VirtIO support.
    Note:
    VirtIO support for Ports 2 and 3 is only available in Production devices or Engineering Samples with the following OPNs:
    • AGIx027R29AxxxxR2
    • AGIx027R29AxxxxR3
    • AGIx027R29BxxxxR3
    • AGIx023R18AxxxxR0
    • AGIx041R29DxxxxR0
    • AGIx041R29DxxxxR1
    • AGMx039R47AxxR0
    For additional details on OPN decoding, refer to the Available Options section of the Agilex™ 7 FPGAs and SoCs Device Overview.