R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 7/08/2024
Public
Document Table of Contents

4.3.1.3.1. Application Logic Guidelines for the Avalon Streaming RX Interface

The following guidelines must be considered by the Application logic:
  • The pX_rx_st_ready_i signal has to be always high. The buffer control and backpressure need to be handled with the RX Flow Control interface. Refer to RX Flow Control Interface for more details.
  • The start of a packet (pX_rx_stN_sop_o) may occur in any of the segments (_stN_).
  • For a single TLP spanning across multiple segments, the application logic needs to process the TLP in the order of the segment index (segment st0 → st1 → st2 → st3 → st0).
  • For multiple TLPs arriving on the same clock cycle, the application logic needs to process the TLPs in the order of the segment index (i.e. segment st0 → st1 → st2 → st3 → st0).
  • The R-Tile PCIe IP does not use segment 2 and segment 3 if segment 0 AND segment 1 are unused. Note that this behavior only applies in Production devices or Engineering Samples with the following OPNs:
    • AGIx027R29AxxxxR2
    • AGIx027R29AxxxxR3
    • AGIx027R29BxxxxR3
    • AGIx023R18AxxxxR0
    • AGIx041R29DxxxxR0
    • AGIx041R29DxxxxR1
    • AGMx039R47AxxR0
    For more details on OPN decoding, refer to the Available Options section of the Agilex™ 7 FPGAs and SoCs Device Overview.
  • The pX_rx_stN_dvalid_o signal can deassert between SOP and EOP. Hence, Application logic must always qualify data whenever pX_rx_stN_dvalid_o is high and not assume that this signal will always be high between pX_rx_stN_sop_o and pX_rx_stN_eop_o.
  • There is a maximum of three SOPs (pX_rx_stN_sop_o) in a single clock cycle. The following table describes the possible combinations across segments:
    Table 57.  Possible Combinations of Three pX_rx_stN_sop_o on a Single Clock Cycle
    pX_rx_st0_sop_o pX_rx_st0_eop_o pX_rx_st1_sop_o pX_rx_st1_eop_o pX_rx_st2_sop_o pX_rx_st2_eop_o pX_rx_st3_sop_o pX_rx_st3_eop_o
    1'b1 1'b1 1'b1 1'b1 1'b1 1'b1 1'b0 1'b0
    1'b1 1'b1 1'b1 1'b1 1'b1 1'b0 1'b0 1'b1
    1'b1 1'b1 1'b1 1'b1 1'b1 1'b0 1'b0 1'b0
    1'b1 1'b1 1'b1 1'b0 1'b0 1'b1 1'b1 1'b1
    1'b1 1'b1 1'b1 1'b0 1'b0 1'b1 1'b1 1'b0
    1'b1 1'b0 1'b0 1'b1 1'b1 1'b1 1'b1 1'b1
    1'b1 1'b0 1'b0 1'b1 1'b1 1'b1 1'b1 1'b0