AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

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ID 683438
Date 2/01/2017
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Document Table of Contents
Document Table of Contents x
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design x
1.1. Design Components 1.2. Design Registers 1.3. Clock and Reset Signals 1.4. Hardware and Software Requirements 1.5. Board Setups 1.6. Testing the Design 1.7. Simulating the Design 1.8. Reference Design Debug Features 1.9. Revision History
1.6. Testing the Design x
1.6.1. Test Commands
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

1.6.1. Test Commands

This reference design provides various Tcl commands to test the Arria® 10 FPGA development board and the Dual XAUI to SFP+ HSMC board in various loopback modes.
Table 6.  TCL CommandsFormat for the TCL command test is TEST <LPBK_POINT> <BURST_SIZE> <NUM_BURSTS> .
Command Mode/Values Description
LPBK_POINT SFPP Loopback at SFP+ cable
BCMPMA Loopback at BCM8727 PMA
BCMXGXS Loopback at BCM8727 XGXS
ALTPMA Loopback at Intel serial PMA
BURST_SIZE Any integer Number of packets in the burst.
NUM_BURSTS Any number greater than 0 Specifies the intended number of bursts.
Each test generates a log file in text file format. View the log to ensure that the traffic monitor does not receive bad packets. The log also provides packet classification and statistics by the MAC TX and RX.
Note: Make sure to reset using the push buttons after each test completes.
Table 7.  Test Commands
Test Command
SFP+ Loopback Test

(External loopback at the SFP+ cable)

TEST SFPP 10000 1
BCM8727 PMA Loopback Test TEST BCMPMA 10000 1
BCM8727 XGXS Loopback Test TEST BCMXGXS 10000 1
PMA Serial Loopback Test TEST ALTPMA 10000 1
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