AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

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ID 683438
Date 2/01/2017
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Document Table of Contents
Document Table of Contents x
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design x
1.1. Design Components 1.2. Design Registers 1.3. Clock and Reset Signals 1.4. Hardware and Software Requirements 1.5. Board Setups 1.6. Testing the Design 1.7. Simulating the Design 1.8. Reference Design Debug Features 1.9. Revision History
1.6. Testing the Design x
1.6.1. Test Commands
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

1.5. Board Setups

Before you run the design, you need to set up the boards.
Figure 4.  Setting Up the Arria® 10 FPGA Development Board

The development board has a stop button for system console testing operations, and reset buttons for the Ethernet subsystem and the Dual XAUI to SFP+ HSMC board.

Figure 5. Setting Up the Dual XAUI to SFP+ HSMC Board

You need the FMC to HSMC adapter board to connect the Arria® 10 FPGA development board to the Dual XAUI to SFP+ HSMC board.

  • Install jumpers at J13 and J14 as shown in the figure above.
  • You must plug the adapter board and HSMC board into the FMCB of the Arria® 10 FPGA development board and install an SFP+ module with a loopback cable in the upper SFP+ slot (CH2).
  • The HSMC board does not require a separate power supply because it draws power from the Arria® 10 FPGA development board.
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