AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

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ID 683438
Date 2/01/2017
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Document Table of Contents
Document Table of Contents x
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design x
1.1. Design Components 1.2. Design Registers 1.3. Clock and Reset Signals 1.4. Hardware and Software Requirements 1.5. Board Setups 1.6. Testing the Design 1.7. Simulating the Design 1.8. Reference Design Debug Features 1.9. Revision History
1.6. Testing the Design x
1.6.1. Test Commands
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

1.7. Simulating the Design

The design provides a testbench for you to verify the design in loopback mode.

The simulation script uses QUARTUS_ROOTDIR environment variable to access Intel simulation libraries. You must set the QUARTUS_ROOTDIR to point to the Quartus® Prime installation path after installation.

Note: If you can't find this environment variable, set the variable manually.
Figure 6. Testbench Block Diagram

To run the simulation, follow these steps:

  1. Download and restore the design.
  2. Navigate to the a10_llmac_xaui_project\testbench directory.
  3. In the TCL Console window, type the following command:
    do tb_run.tcl
  4. When the simulation completes, the Transcript window displays the statistics of the transmitted packets and received packets generated by the simulator.
    Figure 7. TX Statistics
    Figure 8. RX Statistics
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