AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

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ID 683438
Date 2/01/2017
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design x
1.1. Design Components 1.2. Design Registers 1.3. Clock and Reset Signals 1.4. Hardware and Software Requirements 1.5. Board Setups 1.6. Testing the Design 1.7. Simulating the Design 1.8. Reference Design Debug Features 1.9. Revision History
1.6. Testing the Design x
1.6.1. Test Commands
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

1.3. Clock and Reset Signals

The design uses different clock and reset signals for different components.
Table 5.  Clock and Reset Signals
Signal Direction Width Description
refclk1_p Input 1

100 MHz clock source used as IOPLL reference clock and Avalon-MM management clock

csr_clk Input 1 Configuration clock for the Avalon-MM interface, frequency is 100 MHz.
csr_rst_n Input 1 Reset Avalon-MM interface.
tx_312_5_clk Input 1 312.5 MHz clock for MAC TX data path.
rx_312_5_clk Input 1 312.5 MHz clock for MAC RX data path.
tx_156_25_clk Input 1 156.25 MHz clock for MAC TX data path.
rx_156_25_clk Input 1 156.25 MHz clock for MAC RX data path.
tx_rst_n Input 1 Active-low reset for MAC TX data path.
rx_rst_n Input 1 Active-low reset for MAC RX data path.
xgmii_156_25_clk Output 1 156.25 MHz output clock from fPLL.
mac_312_5_clk Output 1 312.5 MHz output clock from fPLL.
pll_ref_clk Input 1 Reference clock for ATX PLL, fPLL, and XAUI PHY.
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