AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

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ID 683438
Date 2/01/2017
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design x
1.1. Design Components 1.2. Design Registers 1.3. Clock and Reset Signals 1.4. Hardware and Software Requirements 1.5. Board Setups 1.6. Testing the Design 1.7. Simulating the Design 1.8. Reference Design Debug Features 1.9. Revision History
1.6. Testing the Design x
1.6.1. Test Commands
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

1.4. Hardware and Software Requirements

Intel uses the following hardware and software to test the design.

Hardware

  • Arria® 10 GX FPGA development kit (revision D)
  • Dual XAUI to SFP+ HSMC board
  • FMC to HSMC adapter board
  • USB Download Cable
  • SFP+ module with loopback cable

Software

  • Quartus® Prime version 16.1 (for hardware testing)
  • ModelSim simulator
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