AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

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ID 683438
Date 2/01/2017
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Document Table of Contents
Document Table of Contents x
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design x
1.1. Design Components 1.2. Design Registers 1.3. Clock and Reset Signals 1.4. Hardware and Software Requirements 1.5. Board Setups 1.6. Testing the Design 1.7. Simulating the Design 1.8. Reference Design Debug Features 1.9. Revision History
1.6. Testing the Design x
1.6.1. Test Commands
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

1.1. Design Components

The reference design consists of three main subsystems: 10GBASE-X Ethernet, Dual XAUI to SFP+ HSMC board, and PC and System Console.
Table 1.  Subsystem Design ComponentsThis table lists the components of the design's subsystems.
Component Description
Low Latency Ethernet 10G MAC IP Core

This IP core handles the flow of data through the XAUI PHY IP core.

  • On transmit path, the MAC accepts client frames and constructs Ethernet frames before forwarding them to the PHY layer.
  • Similarly on the receive path, the MAC accepts Ethernet frames through the PHY layer, performs checks and removes the relevant fields before forwarding the frames to the client.

For this design, the MAC uses the memory-based statistics counters.
XAUI PHY IP Core

The XAUI PHY IP core sets to soft XAUI by default.
Traffic Controller
The traffic controller consists of:
  • Traffic generator—injects client packet bursts into the MAC TX core.
  • Traffic monitor—receives packet bursts from the MAC RX core.

The traffic controller connects to the Avalon-ST single-clock FIFO in the Ethernet subsystem through the Avalon Streaming (Avalon-ST) interface.

Ethernet Packet Generator

This module consists of Avalon Memory-Mapped (Avalon-MM) registers, Ethernet packet generation block, CRC generator, and shift register.

Ethernet Packet Monitor

This module verifies the payload of received packets and collects information from the statistics counters. This consists of Avalon-MM registers and CRC checkers.

MDIO IP Core

This IP core enables you to control the Broadcom PHY BCM8727 chip on the Dual XAUI to SFP+ HSMC board. You can access the external PHY registers through a pair of indirect registers to specify read or write operation, register address, port address, and device address.

JTAG to Avalon Master Bridge

This IP core provides a connection between the System Console and Qsys system through the physical interfaces. The System Console initiates Avalon-MM transactions by sending encoded streams of bytes through the bridge’s physical interfaces.

Reset Controller

This module synchronizes and generates signals as per design requirements.

Avalon-ST Single-Clock FIFO

The Avalon-ST single-clock FIFO buffer receives and transmits data between the MAC and the client. The buffer is 64 bits wide and 512 bits deep. The buffer operates in store-and-forward mode by default. You can configure the buffer to enable the drop-on-error feature. When you enable the drop-on-error feature, the buffer drops the received packets when an error occurs.

Avalon-ST Adapter

This adapter converts the 32-bit Avalon-ST interface to 64 bits and vice verse.
PLL
  • Arria® 10 ATX PLL takes a 156.25 MHz input clock from the on-board oscillator as the clock source for the XAUI PHY.
  • Arria® 10 fPLL takes a 100 MHz input clock from the on-board oscillator and acts as the clock source for the other components in this design.

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