AN794: Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

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ID 683438
Date 2/01/2017
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design x
1.1. Design Components 1.2. Design Registers 1.3. Clock and Reset Signals 1.4. Hardware and Software Requirements 1.5. Board Setups 1.6. Testing the Design 1.7. Simulating the Design 1.8. Reference Design Debug Features 1.9. Revision History
1.6. Testing the Design x
1.6.1. Test Commands
1. Arria® 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design

1.8. Reference Design Debug Features

This design includes a Signal Tap II (STP) file (top.stp) to help you self-debug if you encounter any design issues on the hardware.
The STP file contains 2 instances:
  • Status – monitors the design channel's ready, reset, and PHY statuses.
  • XGMII – monitors the packet condition at XGMII and Avalon-ST interfaces.
Figure 9. Status InstanceThe figure shows that the design channel is ready with resets deasserted.
Figure 10. XGMII InstanceThe figure shows the XGMII (10G) and Avalon-ST (client) interface data path signals to monitor and debug packet conditions during transmission and reception.
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