Visible to Intel only — GUID: rnh1477209644518
Ixiasoft
Visible to Intel only — GUID: rnh1477209644518
Ixiasoft
4. VIP Run-Time Control
All the IP cores have an optional simple run-time control interface that comprises a set of control and status registers, accessible through an Avalon-MM slave port. A run-time control configuration has a mandatory set of three registers for every IP core, followed by any function-specific registers.
Address | Data | Description | |
---|---|---|---|
0 | Bits 31:1 = X | Bit 0 = Go | Control register |
1 | Bits 31:1 = X | Bit 1 = Status | Status register |
2 | Core specific | Interrupt register |
When you enable run-time control, the Go bit gets deasserted by default. If you do not enable run-time control, the Go is asserted by default.
Every IP core retains address 2 in its address space to be used as an interrupt register. However this address is often unused because only some of the IP cores require interrupts.