Video and Image Processing Suite User Guide

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Date 2/12/2021
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Document Table of Contents
Document Table of Contents x
1. About the Video and Image Processing Suite 2. Avalon Streaming Video 3. Clocked Video 4. VIP Run-Time Control 5. Getting Started 6. VIP Connectivity Interfacing 7. Clocked Video Interface IPs 8. 2D FIR II IP Core 9. Mixer II IP Core 10. Clipper II IP Core 11. Color Plane Sequencer II IP Core 12. Color Space Converter II IP Core 13. Chroma Resampler II IP Core 14. Control Synchronizer IP Core 15. Deinterlacer II IP Core 16. Frame Buffer II IP Core 17. Gamma Corrector II IP Core 18. Configurable Guard Bands IP Core 19. Interlacer II IP Core 20. Scaler II IP Core 21. Switch II IP Core 22. Test Pattern Generator II IP Core 23. Trace System IP Core 24. Warp Lite Intel FPGA IP 25. Avalon-ST Video Stream Cleaner IP Core 26. Avalon-ST Video Monitor IP Core 27. VIP IP Core Software Control 28. Security Considerations 29. Video and Image Processing Suite User Guide Archives 30. Document Revision History for the Video and Image Processing Suite User Guide A. Avalon-ST Video Verification IP Suite
1. About the Video and Image Processing Suite x
1.1. Release Information 1.2. Device Family Support 1.3. Latency 1.4. In-System Performance and Resource Guidance 1.5. Stall Behavior and Error Recovery
2. Avalon Streaming Video x
2.1. Avalon-ST Video Configuration Types 2.2. Avalon-ST Video Packet Types 2.3. Avalon-ST Video Operation 2.4. Avalon-ST Video Error Cases
2.2. Avalon-ST Video Packet Types x
2.2.1. Avalon-ST Video Control Packets 2.2.2. Avalon-ST Video Video Packets 2.2.3. Avalon-ST Video User Packets
3. Clocked Video x
3.1. Video Formats
3.1. Video Formats x
3.1.1. Embedded Synchronization Format: Clocked Video Output 3.1.2. Embedded Synchronization Format: Clocked Video Input 3.1.3. Separate Synchronization Format 3.1.4. Video Locked Signal 3.1.5. Clocked Video and 4:2:0 Chroma Subsampling
3.1.1. Embedded Synchronization Format: Clocked Video Output x
3.1.1.1. Clocked Video Output and SDI II TX Interface
3.1.5. Clocked Video and 4:2:0 Chroma Subsampling x
3.1.5.1. Avalon-ST Video Control Packets for 4:2:0 Video 3.1.5.2. 4:2:0 Clocked Video 3.1.5.3. Resampling 4:2:0
5. Getting Started x
5.1. IP Catalog and VIP Parameter Editor 5.2. Installing and Licensing IP Cores
5.1. IP Catalog and VIP Parameter Editor x
5.1.1. Specifying IP Core Parameters and Options
5.2. Installing and Licensing IP Cores x
5.2.1. Intel® FPGA IP Evaluation Mode
6. VIP Connectivity Interfacing x
6.1. Avalon-ST Color Space Mappings
6.1. Avalon-ST Color Space Mappings x
6.1.1. Interfacing with High-Definition Multimedia Interface (HDMI) 6.1.2. Interfacing with DisplayPort 6.1.3. Interfacing with Serial Digital Interface (SDI) 6.1.4. Unsupported SDI Mappings 6.1.5. 12G-SDI
6.1.5. 12G-SDI x
6.1.5.1. 12G-SDI with Clocked Video Input II 6.1.5.2. 12G-SDI with Clocked Video Output II
7. Clocked Video Interface IPs x
7.1. Supported Features for Clocked Video Output II IP 7.2. Control Port 7.3. Clocked Video Input IP Format Detection 7.4. Clocked Video Output IP Video Modes 7.5. Clocked Video Output II Latency Mode 7.6. Generator Lock 7.7. Underflow and Overflow 7.8. Timing Constraints 7.9. Handling Ancillary Packets 7.10. Modules for Clocked Video Input II IP Core 7.11. Clocked Video Input II Signals, Parameters, and Registers 7.12. Clocked Video Output II Signals, Parameters, and Registers
7.3. Clocked Video Input IP Format Detection x
7.3.1. Format Detection in Clocked Video Input II 7.3.2. Interrupts
7.4. Clocked Video Output IP Video Modes x
7.4.1. Interrupts
7.11. Clocked Video Input II Signals, Parameters, and Registers x
7.11.1. Clocked Video Input II Interface Signals 7.11.2. Clocked Video Input II Parameter Settings 7.11.3. Clocked Video Input II Control Registers
7.12. Clocked Video Output II Signals, Parameters, and Registers x
7.12.1. Clocked Video Output II Interface Signals 7.12.2. Clocked Video Output II Parameter Settings 7.12.3. Clocked Video Output II Control Registers
8. 2D FIR II IP Core x
8.1. 2D FIR Filter Processing 8.2. 2D FIR Filter Precision 8.3. 2D FIR Coefficient Specification 8.4. 2D FIR Filter Symmetry 8.5. Result to Output Data Type Conversion 8.6. Edge-Adaptive Sharpen Mode 8.7. 2D FIR Filter Parameter Settings 8.8. 2D FIR Filter Control Registers
8.4. 2D FIR Filter Symmetry x
8.4.1. No Symmetry 8.4.2. Horizontal Symmetry 8.4.3. Vertical Symmetry 8.4.4. Horizontal and Vertical Symmetry 8.4.5. Diagonal Symmetry
8.6. Edge-Adaptive Sharpen Mode x
8.6.1. Edge Detection 8.6.2. Filtering 8.6.3. Precision
9. Mixer II IP Core x
9.1. Alpha Blending 9.2. Mixer II Parameter Settings 9.3. Mixer II Control Registers 9.4. Layer Mapping 9.5. Low-Latency Mode
10. Clipper II IP Core x
10.1. Clipper II Parameter Settings 10.2. Clipper II Control Registers
11. Color Plane Sequencer II IP Core x
11.1. Combining Color Patterns 11.2. Rearranging Color Patterns 11.3. Splitting and Duplicating 11.4. Handling of Subsampled Data 11.5. Handling of Non-Image Avalon-ST Packets 11.6. Color Plane Sequencer Parameter Settings
12. Color Space Converter II IP Core x
12.1. Input and Output Data Types 12.2. Color Space Conversion 12.3. Result of Output Data Type Conversion 12.4. Color Space Converter Parameter Settings 12.5. Color Space Conversion Control Registers
12.2. Color Space Conversion x
12.2.1. Predefined Conversions
13. Chroma Resampler II IP Core x
13.1. Chroma Resampler Algorithms 13.2. Chroma Resampler Parameter Settings 13.3. Chroma Resampler Control Registers
13.1. Chroma Resampler Algorithms x
13.1.1. Nearest Neighbor 13.1.2. Bilinear 13.1.3. Filtered
14. Control Synchronizer IP Core x
14.1. Using the Control Synchronizer IP Core 14.2. Control Synchronizer Parameter Settings 14.3. Control Synchronizer Control Registers
15. Deinterlacer II IP Core x
15.1. Deinterlacing Algorithm Options 15.2. Deinterlacing Algorithms 15.3. Run-time Control 15.4. Pass-Through Mode for Progressive Frames 15.5. Cadence Detection (Motion Adaptive Deinterlacing Only) 15.6. Avalon-MM Interface to Memory 15.7. Motion Adaptive Mode Bandwidth Requirements 15.8. Avalon-ST Video Support 15.9. 4K Video Passthrough Support 15.10. Behavior When Unexpected Fields are Received 15.11. Handling of Avalon-ST Video Control Packets 15.12. Deinterlacer II Parameter Settings 15.13. Deinterlacing Control Registers
15.2. Deinterlacing Algorithms x
15.2.1. Vertical Interpolation (Bob) 15.2.2. Field Weaving (Weave) 15.2.3. Motion Adaptive 15.2.4. Motion Adaptive High Quality (Sobel Edge Interpolation)
15.9. 4K Video Passthrough Support x
15.9.1. Approach A 15.9.2. Approach B
15.13. Deinterlacing Control Registers x
15.13.1. Scene Change Motion Multiplier Value 15.13.2. Tuning Motion Shift and Motion Scale Registers
16. Frame Buffer II IP Core x
16.1. Double Buffering 16.2. Triple Buffering 16.3. Locked Frame Rate Conversion 16.4. Handling of Avalon-ST Video Control Packets and User Packets 16.5. Frame Buffer Parameter Settings 16.6. Frame Buffer Application Examples 16.7. Frame Buffer Control Registers
16.3. Locked Frame Rate Conversion x
16.3.1. Converting Frame Rates
16.7. Frame Buffer Control Registers x
16.7.1. Frame Writer Only Mode 16.7.2. Frame Reader Only Mode 16.7.3. Memory Map for Frame Reader or Writer Configurations
17. Gamma Corrector II IP Core x
17.1. Gamma Corrector Parameter Settings 17.2. Gamma Corrector Control Registers
18. Configurable Guard Bands IP Core x
18.1. Guard Bands Parameter Settings 18.2. Configurable Guard Bands Control Registers
19. Interlacer II IP Core x
19.1. Interlacer Parameter Settings 19.2. Interlacer Control Registers
20. Scaler II IP Core x
20.1. Nearest Neighbor Algorithm 20.2. Bilinear Algorithm 20.3. Polyphase and Bicubic Algorithm 20.4. Edge-Adaptive Scaling Algorithm 20.5. Scaler II Parameter Settings 20.6. Scaler II Control Registers
20.2. Bilinear Algorithm x
20.2.1. Bilinear Algorithmic Description
20.3. Polyphase and Bicubic Algorithm x
20.3.1. Double-Buffering 20.3.2. Polyphase Algorithmic Description 20.3.3. Choosing and Loading Coefficients
21. Switch II IP Core x
21.1. Switch II Parameter Settings 21.2. Switch II Control Registers
22. Test Pattern Generator II IP Core x
22.1. Test Patterns 22.2. Output Subsampling and Color Space 22.3. Generation of Avalon-ST Video Control Packets and Run-Time Control 22.4. Test Pattern Generator II Parameter Settings 22.5. Test Pattern Generator II Control Registers
22.1. Test Patterns x
22.1.1. Color Bars 22.1.2. Grayscale Bars 22.1.3. Black and White Bars 22.1.4. SDI Pathological 22.1.5. Uniform Background
23. Trace System IP Core x
23.1. Trace System Parameter Settings 23.2. Trace System Signals 23.3. Operating the Trace System from System Console
23.3. Operating the Trace System from System Console x
23.3.1. Loading the Project and Connecting to the Hardware 23.3.2. Trace Within System Console 23.3.3. TCL Shell Commands
24. Warp Lite Intel FPGA IP x
24.1. Warp Lite IP Release Information 24.2. About Image Warping 24.3. About the Warp Lite Intel FPGA IP 24.4. Operating the Warp Lite IP 24.5. Warp Lite IP Parameters 24.6. Warp Lite IP Control Registers' Map 24.7. Warp Lite IP Line Store 24.8. Warp Lite IP API
24.3. About the Warp Lite Intel FPGA IP x
24.3.1. Warp Definition Equations 24.3.2. Resampling and Interpolation
24.3.1. Warp Definition Equations x
24.3.1.1. Transform Matrix and Keystone Region Corners 24.3.1.2. Horizontal Flip Equation
24.7. Warp Lite IP Line Store x
24.7.1. Line Store RAM Utilization 24.7.2. Buffer Ingress and Egress Overlap
25. Avalon-ST Video Stream Cleaner IP Core x
25.1. Avalon-ST Video Protocol 25.2. Repairing Non-Ideal and Error Cases 25.3. Avalon-ST Video Stream Cleaner Parameter Settings 25.4. Avalon-ST Video Stream Cleaner Control Registers
26. Avalon-ST Video Monitor IP Core x
26.1. Packet Visualization 26.2. Monitor Settings 26.3. Avalon-ST Video Monitor Parameter Settings 26.4. Avalon-ST Video Monitor Control Registers
27. VIP IP Core Software Control x
27.1. HAL Device Drivers for Nios II SBT
28. Security Considerations x
28.1. Using Avalon-ST Video Monitor Debug Tools 28.2. Configuring Memory Subsystems
A. Avalon-ST Video Verification IP Suite x
A.1. Avalon-ST Video Class Library A.2. Example Tests A.3. Complete Class Reference A.4. Data Format
A.2. Example Tests x
A.2.1. Generating the Testbench Netlist A.2.2. Running the Test in Intel® Quartus® Prime Standard Edition A.2.3. Running the Test in Intel® Quartus® Prime Pro Edition A.2.4. Viewing the Video File A.2.5. Verification Files A.2.6. Constrained Random Test
A.2.5. Verification Files x
A.2.5.1. bfm_drivers.sv A.2.5.2. nios_control_model.sv
A.3. Complete Class Reference x
A.3.1. c_av_st_video_control A.3.2. c_av_st_video_data A.3.3. c_av_st_video_file_io A.3.4. c_av_st_video_item A.3.5. c_av_st_video_source_sink_base A.3.6. c_av_st_video_sink_bfm_’SINK A.3.7. c_av_st_video_source_bfm_’SOURCE A.3.8. c_av_st_video_user_packet A.3.9. c_pixel A.3.10. av_mm_transaction A.3.11. av_mm_master_bfm_`MASTER_NAME A.3.12. av_mm_slave_bfm_`SLAVE_NAME A.3.13. av_mm_control_register A.3.14. av_mm_control_base
1. About the Video and Image Processing Suite
2. Avalon Streaming Video
3. Clocked Video
4. VIP Run-Time Control
5. Getting Started
6. VIP Connectivity Interfacing
7. Clocked Video Interface IPs
8. 2D FIR II IP Core
9. Mixer II IP Core
10. Clipper II IP Core
11. Color Plane Sequencer II IP Core
12. Color Space Converter II IP Core
13. Chroma Resampler II IP Core
14. Control Synchronizer IP Core
15. Deinterlacer II IP Core
16. Frame Buffer II IP Core
17. Gamma Corrector II IP Core
18. Configurable Guard Bands IP Core
19. Interlacer II IP Core
20. Scaler II IP Core
21. Switch II IP Core
22. Test Pattern Generator II IP Core
23. Trace System IP Core
24. Warp Lite Intel FPGA IP
25. Avalon-ST Video Stream Cleaner IP Core
26. Avalon-ST Video Monitor IP Core
27. VIP IP Core Software Control
28. Security Considerations
29. Video and Image Processing Suite User Guide Archives
30. Document Revision History for the Video and Image Processing Suite User Guide
A. Avalon-ST Video Verification IP Suite

7.11.1. Clocked Video Input II Interface Signals

Table 22.  Clocked Video Input II Signals
Signal Direction Description
main_reset_reset Input The IP core asynchronously resets when you assert this signal. You must deassert this signal synchronously to the rising edge of the clock signal.
main_clock_clk Input The main system clock. The IP core operates on the rising edge of this signal.
dout_data Output dout port Avalon-ST data bus. This bus enables the transfer of pixel data out of the IP core.
dout_endofpacket Output dout port Avalon-ST endofpacket signal. This signal is asserted when the IP core is ending a frame.
dout_ready Input dout port Avalon-ST ready signal. The downstream device asserts this signal when it is able to receive data.
dout_startofpacket Output dout port Avalon-ST startofpacket signal. This signal is asserted when the IP core is starting a new frame.
dout_valid Output dout port Avalon-ST valid signal. This signal is asserted when the IP core produces data.
dout_empty Output dout port Avalon-ST empty signal. This signal has a non-zero value only when you set the Number of pixels in parallel parameter to be greater than 1. This signal specifies the number of pixel positions which are empty at the end of the dout_endofpacket signal.
status_update_int Output control slave port Avalon-MM interrupt signal. When asserted, the status registers of the IP core have been updated and the master must read them to determine what has occurred.
Note: Present only if you turn on Use control port.
vid_clk Input Clocked video clock. All the video input signals are synchronous to this clock.
vid_data Input Clocked video data bus. This bus enables the transfer of video data into the IP core.
vid_de Input Clocked video data enable signal. The driving core asserts this signal to indicate that the data on vid_data is part of the active picture region of an incoming video. This signal must be driven for correct operation of the IP core.
Note: For separate synchronization mode only.
vid_datavalid Input Enabling signal for the CVI II IP core. The IP core only reads the vid_data, vid_de, vid_h_sync, vid_v_sync, vid_std, and vid_f signals when vid_datavalid is 1. This signal allows the CVI II IP core to support oversampling during when the video runs at a higher rate than the pixel clock.
Note: If you are not oversampling your input video, tie this signal high.
vid_locked Input Clocked video locked signal. Assert this signal when a stable video stream is present on the input. Deassert this signal when the video stream is removed.

When 0, this signal triggers an early end of output frame packet and does not reset the internal registers. When this signal recovers after 0, if the system is not reset from outside, the first frame may have leftover pixels from the lock-lost frame,

vid_f Input Clocked video field signal. For interlaced input, this signal distinguishes between field 0 and field 1. For progressive video, you must deassert this signal.
Note: For separate synchronization mode only.
vid_v_sync Input Clocked video vertical synchronization signal. Assert this signal during the vertical synchronization period of the video stream.
Note: For separate synchronization mode only.
vid_h_sync Input Clocked video horizontal synchronization signal. Assert this signal during the horizontal synchronization period of the video stream.
Note: For separate synchronization mode only.
vid_hd_sdn Input Clocked video color plane format selection signal . This signal distinguishes between sequential (when low) and parallel (when high) color plane formats.
Note: For run-time switching of color plane transmission formats mode only.
vid_std Input Video standard bus. Can be connected to the rx_std signal of the SDI IP core (or any other interface) to read from the Standard register.
vid_color_encoding Input This signal is captured in the Color Pattern register and does not affect the functioning of the IP core. It provides a mechanism for control processors to read incoming color space information if the IP core (e.g. HDMI RX core) driving the CVI II does not provide such an interface.

Tie this signal to low if no equivalent signal is available from the IP core driving CVI II.

vid_bit_width Input This signal is captured in the Color Pattern register and does not affect the functioning of the IP core. It provides a mechanism for control processors to read incoming video bit width information if the IP core (e.g. HDMI RX core) driving the CVI II does not provide such an interface.

Tie this signal to low if no equivalent signal is available from the IP core driving CVI II.

vid_total_sample_count Input The IP core creates this signal if you do not turn on the Extract the total resolution parameter. The CVI II IP core operates using this signal as the total horizontal resolution instead of an internally detected version.
Vid_total_line_count Input The IP core creates this signal if you do not turn on the Extract the total resolution parameter. The CVI II IP core operates using this signal as the total vertical resolution instead of an internally detected version.
sof Output Start of frame signal. A change of 0 to 1 indicates the start of the video frame as configured by the SOF registers. Connecting this signal to a CVO IP core allows the function to synchronize its output video to this signal.
sof_locked Output Start of frame locked signal. When asserted, the sof signal is valid and can be used.
refclk_div Output A single cycle pulse in-line with the rising edge of the h sync.
clipping Output Clocked video clipping signal. A signal corresponding to the clipping bit of the Status register synchronized to vid_clk.

This signal is for information only and no action is required if it is asserted.

padding Output Clocked video padding signal. A signal corresponding to the padding bit of the Status register synchronized to vid_clk.

This signal is for information only and no action is required if it is asserted.

overflow Output Clocked video overflow signal. A signal corresponding to the overflow sticky bit of the Status register synchronized to vid_clk. This signal is for information only and no action is required if it is asserted.
Note: Present only if you turn on Use control port.
vid_hdmi_duplication[3:0] Input If you select Remove duplicate pixels in the parameter, this 4-bit bus is added to the CVI II interface. You can drive this bus based on the number of times each pixel is duplicated in the stream (HDMI-standard compliant).
Table 23.  Control Signals for CVI II IP Cores
Signal Direction Description
av_address Input control slave port Avalon-MM address bus. Specifies a word offset into the slave address space.
Note: Present only if you turn on Use control port.
av_read Input control slave port Avalon-MM read signal. When you assert this signal, the control port drives new data onto the read data bus.
Note: Present only if you turn on Use control port.
av_readdata Output control slave port Avalon-MM read data bus. These output lines are used for read transfers.
Note: Present only if you turn on Use control port.
av_waitrequest Output
control slave port Avalon-MM wait request bus. This signal indicates that the slave is stalling the master transaction.
Note: Present only if you turn on Use control port.
av_write Input control slave port Avalon-MM write signal. When you assert this signal, the control port accepts new data from the write data bus.
Note: Present only if you turn on Use control port.
av_writedata Input control slave port Avalon-MM write data bus. These input lines are used for write transfers.
Note: Present only if you turn on Use control port.
av_byteenable Input control slave port Avalon-MM byteenable bus. These lines indicate which bytes are selected for write and read transactions.

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