Video and Image Processing Suite User Guide

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Date 2/12/2021
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Document Table of Contents
Document Table of Contents x
1. About the Video and Image Processing Suite 2. Avalon Streaming Video 3. Clocked Video 4. VIP Run-Time Control 5. Getting Started 6. VIP Connectivity Interfacing 7. Clocked Video Interface IPs 8. 2D FIR II IP Core 9. Mixer II IP Core 10. Clipper II IP Core 11. Color Plane Sequencer II IP Core 12. Color Space Converter II IP Core 13. Chroma Resampler II IP Core 14. Control Synchronizer IP Core 15. Deinterlacer II IP Core 16. Frame Buffer II IP Core 17. Gamma Corrector II IP Core 18. Configurable Guard Bands IP Core 19. Interlacer II IP Core 20. Scaler II IP Core 21. Switch II IP Core 22. Test Pattern Generator II IP Core 23. Trace System IP Core 24. Warp Lite Intel FPGA IP 25. Avalon-ST Video Stream Cleaner IP Core 26. Avalon-ST Video Monitor IP Core 27. VIP IP Core Software Control 28. Security Considerations 29. Video and Image Processing Suite User Guide Archives 30. Document Revision History for the Video and Image Processing Suite User Guide A. Avalon-ST Video Verification IP Suite
1. About the Video and Image Processing Suite x
1.1. Release Information 1.2. Device Family Support 1.3. Latency 1.4. In-System Performance and Resource Guidance 1.5. Stall Behavior and Error Recovery
2. Avalon Streaming Video x
2.1. Avalon-ST Video Configuration Types 2.2. Avalon-ST Video Packet Types 2.3. Avalon-ST Video Operation 2.4. Avalon-ST Video Error Cases
2.2. Avalon-ST Video Packet Types x
2.2.1. Avalon-ST Video Control Packets 2.2.2. Avalon-ST Video Video Packets 2.2.3. Avalon-ST Video User Packets
3. Clocked Video x
3.1. Video Formats
3.1. Video Formats x
3.1.1. Embedded Synchronization Format: Clocked Video Output 3.1.2. Embedded Synchronization Format: Clocked Video Input 3.1.3. Separate Synchronization Format 3.1.4. Video Locked Signal 3.1.5. Clocked Video and 4:2:0 Chroma Subsampling
3.1.1. Embedded Synchronization Format: Clocked Video Output x
3.1.1.1. Clocked Video Output and SDI II TX Interface
3.1.5. Clocked Video and 4:2:0 Chroma Subsampling x
3.1.5.1. Avalon-ST Video Control Packets for 4:2:0 Video 3.1.5.2. 4:2:0 Clocked Video 3.1.5.3. Resampling 4:2:0
5. Getting Started x
5.1. IP Catalog and VIP Parameter Editor 5.2. Installing and Licensing IP Cores
5.1. IP Catalog and VIP Parameter Editor x
5.1.1. Specifying IP Core Parameters and Options
5.2. Installing and Licensing IP Cores x
5.2.1. Intel® FPGA IP Evaluation Mode
6. VIP Connectivity Interfacing x
6.1. Avalon-ST Color Space Mappings
6.1. Avalon-ST Color Space Mappings x
6.1.1. Interfacing with High-Definition Multimedia Interface (HDMI) 6.1.2. Interfacing with DisplayPort 6.1.3. Interfacing with Serial Digital Interface (SDI) 6.1.4. Unsupported SDI Mappings 6.1.5. 12G-SDI
6.1.5. 12G-SDI x
6.1.5.1. 12G-SDI with Clocked Video Input II 6.1.5.2. 12G-SDI with Clocked Video Output II
7. Clocked Video Interface IPs x
7.1. Supported Features for Clocked Video Output II IP 7.2. Control Port 7.3. Clocked Video Input IP Format Detection 7.4. Clocked Video Output IP Video Modes 7.5. Clocked Video Output II Latency Mode 7.6. Generator Lock 7.7. Underflow and Overflow 7.8. Timing Constraints 7.9. Handling Ancillary Packets 7.10. Modules for Clocked Video Input II IP Core 7.11. Clocked Video Input II Signals, Parameters, and Registers 7.12. Clocked Video Output II Signals, Parameters, and Registers
7.3. Clocked Video Input IP Format Detection x
7.3.1. Format Detection in Clocked Video Input II 7.3.2. Interrupts
7.4. Clocked Video Output IP Video Modes x
7.4.1. Interrupts
7.11. Clocked Video Input II Signals, Parameters, and Registers x
7.11.1. Clocked Video Input II Interface Signals 7.11.2. Clocked Video Input II Parameter Settings 7.11.3. Clocked Video Input II Control Registers
7.12. Clocked Video Output II Signals, Parameters, and Registers x
7.12.1. Clocked Video Output II Interface Signals 7.12.2. Clocked Video Output II Parameter Settings 7.12.3. Clocked Video Output II Control Registers
8. 2D FIR II IP Core x
8.1. 2D FIR Filter Processing 8.2. 2D FIR Filter Precision 8.3. 2D FIR Coefficient Specification 8.4. 2D FIR Filter Symmetry 8.5. Result to Output Data Type Conversion 8.6. Edge-Adaptive Sharpen Mode 8.7. 2D FIR Filter Parameter Settings 8.8. 2D FIR Filter Control Registers
8.4. 2D FIR Filter Symmetry x
8.4.1. No Symmetry 8.4.2. Horizontal Symmetry 8.4.3. Vertical Symmetry 8.4.4. Horizontal and Vertical Symmetry 8.4.5. Diagonal Symmetry
8.6. Edge-Adaptive Sharpen Mode x
8.6.1. Edge Detection 8.6.2. Filtering 8.6.3. Precision
9. Mixer II IP Core x
9.1. Alpha Blending 9.2. Mixer II Parameter Settings 9.3. Mixer II Control Registers 9.4. Layer Mapping 9.5. Low-Latency Mode
10. Clipper II IP Core x
10.1. Clipper II Parameter Settings 10.2. Clipper II Control Registers
11. Color Plane Sequencer II IP Core x
11.1. Combining Color Patterns 11.2. Rearranging Color Patterns 11.3. Splitting and Duplicating 11.4. Handling of Subsampled Data 11.5. Handling of Non-Image Avalon-ST Packets 11.6. Color Plane Sequencer Parameter Settings
12. Color Space Converter II IP Core x
12.1. Input and Output Data Types 12.2. Color Space Conversion 12.3. Result of Output Data Type Conversion 12.4. Color Space Converter Parameter Settings 12.5. Color Space Conversion Control Registers
12.2. Color Space Conversion x
12.2.1. Predefined Conversions
13. Chroma Resampler II IP Core x
13.1. Chroma Resampler Algorithms 13.2. Chroma Resampler Parameter Settings 13.3. Chroma Resampler Control Registers
13.1. Chroma Resampler Algorithms x
13.1.1. Nearest Neighbor 13.1.2. Bilinear 13.1.3. Filtered
14. Control Synchronizer IP Core x
14.1. Using the Control Synchronizer IP Core 14.2. Control Synchronizer Parameter Settings 14.3. Control Synchronizer Control Registers
15. Deinterlacer II IP Core x
15.1. Deinterlacing Algorithm Options 15.2. Deinterlacing Algorithms 15.3. Run-time Control 15.4. Pass-Through Mode for Progressive Frames 15.5. Cadence Detection (Motion Adaptive Deinterlacing Only) 15.6. Avalon-MM Interface to Memory 15.7. Motion Adaptive Mode Bandwidth Requirements 15.8. Avalon-ST Video Support 15.9. 4K Video Passthrough Support 15.10. Behavior When Unexpected Fields are Received 15.11. Handling of Avalon-ST Video Control Packets 15.12. Deinterlacer II Parameter Settings 15.13. Deinterlacing Control Registers
15.2. Deinterlacing Algorithms x
15.2.1. Vertical Interpolation (Bob) 15.2.2. Field Weaving (Weave) 15.2.3. Motion Adaptive 15.2.4. Motion Adaptive High Quality (Sobel Edge Interpolation)
15.9. 4K Video Passthrough Support x
15.9.1. Approach A 15.9.2. Approach B
15.13. Deinterlacing Control Registers x
15.13.1. Scene Change Motion Multiplier Value 15.13.2. Tuning Motion Shift and Motion Scale Registers
16. Frame Buffer II IP Core x
16.1. Double Buffering 16.2. Triple Buffering 16.3. Locked Frame Rate Conversion 16.4. Handling of Avalon-ST Video Control Packets and User Packets 16.5. Frame Buffer Parameter Settings 16.6. Frame Buffer Application Examples 16.7. Frame Buffer Control Registers
16.3. Locked Frame Rate Conversion x
16.3.1. Converting Frame Rates
16.7. Frame Buffer Control Registers x
16.7.1. Frame Writer Only Mode 16.7.2. Frame Reader Only Mode 16.7.3. Memory Map for Frame Reader or Writer Configurations
17. Gamma Corrector II IP Core x
17.1. Gamma Corrector Parameter Settings 17.2. Gamma Corrector Control Registers
18. Configurable Guard Bands IP Core x
18.1. Guard Bands Parameter Settings 18.2. Configurable Guard Bands Control Registers
19. Interlacer II IP Core x
19.1. Interlacer Parameter Settings 19.2. Interlacer Control Registers
20. Scaler II IP Core x
20.1. Nearest Neighbor Algorithm 20.2. Bilinear Algorithm 20.3. Polyphase and Bicubic Algorithm 20.4. Edge-Adaptive Scaling Algorithm 20.5. Scaler II Parameter Settings 20.6. Scaler II Control Registers
20.2. Bilinear Algorithm x
20.2.1. Bilinear Algorithmic Description
20.3. Polyphase and Bicubic Algorithm x
20.3.1. Double-Buffering 20.3.2. Polyphase Algorithmic Description 20.3.3. Choosing and Loading Coefficients
21. Switch II IP Core x
21.1. Switch II Parameter Settings 21.2. Switch II Control Registers
22. Test Pattern Generator II IP Core x
22.1. Test Patterns 22.2. Output Subsampling and Color Space 22.3. Generation of Avalon-ST Video Control Packets and Run-Time Control 22.4. Test Pattern Generator II Parameter Settings 22.5. Test Pattern Generator II Control Registers
22.1. Test Patterns x
22.1.1. Color Bars 22.1.2. Grayscale Bars 22.1.3. Black and White Bars 22.1.4. SDI Pathological 22.1.5. Uniform Background
23. Trace System IP Core x
23.1. Trace System Parameter Settings 23.2. Trace System Signals 23.3. Operating the Trace System from System Console
23.3. Operating the Trace System from System Console x
23.3.1. Loading the Project and Connecting to the Hardware 23.3.2. Trace Within System Console 23.3.3. TCL Shell Commands
24. Warp Lite Intel FPGA IP x
24.1. Warp Lite IP Release Information 24.2. About Image Warping 24.3. About the Warp Lite Intel FPGA IP 24.4. Operating the Warp Lite IP 24.5. Warp Lite IP Parameters 24.6. Warp Lite IP Control Registers' Map 24.7. Warp Lite IP Line Store 24.8. Warp Lite IP API
24.3. About the Warp Lite Intel FPGA IP x
24.3.1. Warp Definition Equations 24.3.2. Resampling and Interpolation
24.3.1. Warp Definition Equations x
24.3.1.1. Transform Matrix and Keystone Region Corners 24.3.1.2. Horizontal Flip Equation
24.7. Warp Lite IP Line Store x
24.7.1. Line Store RAM Utilization 24.7.2. Buffer Ingress and Egress Overlap
25. Avalon-ST Video Stream Cleaner IP Core x
25.1. Avalon-ST Video Protocol 25.2. Repairing Non-Ideal and Error Cases 25.3. Avalon-ST Video Stream Cleaner Parameter Settings 25.4. Avalon-ST Video Stream Cleaner Control Registers
26. Avalon-ST Video Monitor IP Core x
26.1. Packet Visualization 26.2. Monitor Settings 26.3. Avalon-ST Video Monitor Parameter Settings 26.4. Avalon-ST Video Monitor Control Registers
27. VIP IP Core Software Control x
27.1. HAL Device Drivers for Nios II SBT
28. Security Considerations x
28.1. Using Avalon-ST Video Monitor Debug Tools 28.2. Configuring Memory Subsystems
A. Avalon-ST Video Verification IP Suite x
A.1. Avalon-ST Video Class Library A.2. Example Tests A.3. Complete Class Reference A.4. Data Format
A.2. Example Tests x
A.2.1. Generating the Testbench Netlist A.2.2. Running the Test in Intel® Quartus® Prime Standard Edition A.2.3. Running the Test in Intel® Quartus® Prime Pro Edition A.2.4. Viewing the Video File A.2.5. Verification Files A.2.6. Constrained Random Test
A.2.5. Verification Files x
A.2.5.1. bfm_drivers.sv A.2.5.2. nios_control_model.sv
A.3. Complete Class Reference x
A.3.1. c_av_st_video_control A.3.2. c_av_st_video_data A.3.3. c_av_st_video_file_io A.3.4. c_av_st_video_item A.3.5. c_av_st_video_source_sink_base A.3.6. c_av_st_video_sink_bfm_’SINK A.3.7. c_av_st_video_source_bfm_’SOURCE A.3.8. c_av_st_video_user_packet A.3.9. c_pixel A.3.10. av_mm_transaction A.3.11. av_mm_master_bfm_`MASTER_NAME A.3.12. av_mm_slave_bfm_`SLAVE_NAME A.3.13. av_mm_control_register A.3.14. av_mm_control_base
1. About the Video and Image Processing Suite
2. Avalon Streaming Video
3. Clocked Video
4. VIP Run-Time Control
5. Getting Started
6. VIP Connectivity Interfacing
7. Clocked Video Interface IPs
8. 2D FIR II IP Core
9. Mixer II IP Core
10. Clipper II IP Core
11. Color Plane Sequencer II IP Core
12. Color Space Converter II IP Core
13. Chroma Resampler II IP Core
14. Control Synchronizer IP Core
15. Deinterlacer II IP Core
16. Frame Buffer II IP Core
17. Gamma Corrector II IP Core
18. Configurable Guard Bands IP Core
19. Interlacer II IP Core
20. Scaler II IP Core
21. Switch II IP Core
22. Test Pattern Generator II IP Core
23. Trace System IP Core
24. Warp Lite Intel FPGA IP
25. Avalon-ST Video Stream Cleaner IP Core
26. Avalon-ST Video Monitor IP Core
27. VIP IP Core Software Control
28. Security Considerations
29. Video and Image Processing Suite User Guide Archives
30. Document Revision History for the Video and Image Processing Suite User Guide
A. Avalon-ST Video Verification IP Suite

A.2.6. Constrained Random Test

The constrained random test example is easily assembled using the class library.
Note: The steps to run the constrained random are described at the start of this section.
Figure 87. Example of a Constrained Random Test EnvironmentThe figure below shows the constrained random test environment structure.

Randomized video, control, and user packets are generated using the SystemVerilog’s built-in constrained random features. The DUT processes the video packets and the scoreboard determines a test pass or fail result.

test.sv comprises the following code sections:

Declaration Description
1 Object Declarations   
18 c_av_st_video_control #(`BITS_PER_SYMBOL, `CHANNELS_PER_PIXEL) video_control_pkt1,  video_control_pkt2;
19 c_av_st_video_control #(`BITS_PER_SYMBOL, `CHANNELS_PER_PIXEL) video_control_dut, video_control_golden;
20 c_av_st_video_data #(`BITS_PER_SYMBOL, `CHANNELS_PER_PIXEL) video_data_dut, video_data_scoreboard;
21 c_av_st_video_data #(`BITS_PER_SYMBOL, `CHANNELS_PER_PIXEL) dut_video_pkt, scoreboard_video_pkt;
22 c_av_st_video_data video_data_real_pkt1, video_data_real_pkt2 ;
23 c_av_st_video_item dut_pkt;
24 c_av_st_video_item scoreboard_pkt;

Declare some objects to be used later in the test. Notice that the number of pixels in parallel is not needed in these definitions as that is abstracted away from the user and handled via the classes in av_st_video_source_bfm_class.sv and av_st_video_sink_bfm_class.sv.

Note that the video item class is the base class, so could hold objects of any of the more specialized classes, such as control or video data.

2 Mailbox Declarations Description 
27 mailbox #(c_av_st_video_item) m_video_items_for_scoreboard[1];
28 
29 int input_frame_count = 0;
30 
31 initial
32 begin
33
34 // Construct the 0th element of the video items mailbox array
35 m_video_items_for_scoreboard[0] = new(0);
 The bfm_drivers.sv file contains mailbox declarations required for transmission and receipt of video packets, but the test harness requires a mailbox for the scoreboard. It is declared in line 27 and constructed at time zero in line 35.
3 Start the Source and Sink BFMs Description 
61 #0 // Delta-cycle delay to ensure the BFM drivers were constructed in bfm_drivers.sv
62 fork // .start() calls to the VIP BFM drivers are blocking. Fork the calls.
63 st_source_bfm_0.start();
64 st_sink_bfm_0.start(av_st_clk);
65 join_none;

The source and sink BFMs must be started. Once started, the source will wait for objects for sending to be pushed into its mailbox whilst the sink will push objects into its mailbox when one is received from the DUT.

4 Stimulus—Start Producing Control and Video Packets Description 
109 produce_control_pkt(add_to_scoreboard,`MAX_WIDTH,`MAX_HEIGHT,quantization,ctrl_width,ctrl_height,ctrl_interlacing);
110
111 // Don't add video packet to scoreboard if a drop packet will be IMMEDIATELY following it
112 if (`COLOR_PLANES_ARE_IN_PARALLEL == 1)
113 produce_video_pkt((ctrl_width), ctrl_height, add_to_scoreboard);
114 else
115 produce_video_pkt((ctrl_width*`CHANNELS_PER_PIXEL), ctrl_height, add_to_scoreboard);

In the main loop calls are made to the tasks in class_library/tasks.sv to produce randomly sized control packets with matching video packets.

4 Packet Checker—Checking Produced Control and Video Packets Against the Scoreboard Description 
161 while ((op_pkts_seen <= (input_frame_count*2)) && !timeout)
162 begin : main_checker_loop  // NB x2 for control packets
163
164 @(posedge(av_st_clk));
165
166 if (m_video_items_for_sink_bfm[0][0].try_get(dut_pkt) == 1)
167 begin : packet_found

The corresponding loop to the stimulus loop is the checker code. This polls the sink’s mailbox for video items, categorizes according to type and to which packet type is expected, compares video packets to those previously input and then marks the packet as pass or fail accordingly.

Line 161 shows that the checker loop runs until twice the input frame count has been seen (control plus video packet per input frame) and uses the try_get() call on the sink mailbox in line 166 to check for DUT packets. 

174 // DUT has output a Video packet
175 if (dut_pkt.get_packet_type() != control_packet)
176 begin : possible_video_packet_found
177
178 if (dut_pkt.get_packet_type() == video_packet)
179 begin : video_packet_found
180
181 dut_video_pkt = c_av_st_video_data'(dut_pkt); //'
182
183 // First output packets should be colour bars :
184 if ((op_pkts_seen <= `MIXER_NUM_TPG_OUTPUT_FRAMES*2) && !expecting_dut_control_packet)
185 begin : absorb_colour_bars
186 $display("%t   DUT DOUT : PASS - DUT output an assumed mixer background pattern video packet %0d(VIDEO length == %0d).",$time,op_pkts_seen,dut_video_pkt.get_length());
187 end 
188
189 else
190 begin : mixed_packets
191
192 // Sledgehammer approach for example test - search all input frames for the one currently output:
193 matching_frame = 0;
194 frames_to_check = m_video_items_for_scoreboard[0].num();
195 while (frames_to_check>0 && !matching_frame) begin
196 frames_to_check--;
197 m_video_items_for_scoreboard[0].get(scoreboard_pkt);
198 if (scoreboard_pkt.get_packet_type() == video_packet) begin
199 scoreboard_video_pkt = c_av_st_video_data'(scoreboard_pkt); //'
200 if (dut_video_pkt.silent_compare(scoreboard_video_pkt) == 1)
201 matching_frame = 1;
202
203 m_tmp.put(scoreboard_pkt);
204 end
205 end

Once the packet type is determined (lines 174-179) it is cast to an object of the corresponding type (see line 181).

As earlier described, in testbench/nios2_control_model.sv, the Mixer II is set up to offset the output video from the frame buffer by zero pixels for constrained random testing, so line 184 below shows that we expect to see one frame of test pattern (while the frame buffer receives and buffers the first input frame) followed by the video packets.

The code from lines 195-205 iterates through every item in the scoreboard, casting to a video packet type as required, before comparing to the DUT video packet in line 200 (using the built-in silent_compare method from class_library/av_st_video_classes, which does not generate output if the packets do not match). A flag is set if a match is found and the scoreboard packet is pushed onto a temporary mailbox store. After the search, all scoreboard packets are popped off the temporary store ready for comparing with subsequent video frames.

Control packets are compared against a golden one in a similar way.

Level Two Title