AN 739: Altera 1588 System Solution

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ID 683410
Date 1/28/2016
Public
Document Table of Contents
Document Table of Contents x
1. Altera 1588 System Solution
1. Altera 1588 System Solution x
1.1. Altera 1588 System Level Overview 1.2. Precision Time Protocol (PTP) Concept in A 1588 System 1.3. Reference Design Walk-through 1.4. System Architecture 1.5. Altera 1588 System Solution Document Revision History
1.2. Precision Time Protocol (PTP) Concept in A 1588 System x
1.2.1. Understanding the Different PTP Clocks 1.2.2. Precision Time Protocol (PTP) Synchronization Process 1.2.3. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System 1.2.4. Functional Flow For A 1588 Transparent Clock Master/Slave Mode System 1.2.5. Functional Flow for A 1588 Boundary Clock Mode System 1.2.6. Timestamp Packet Functional Flow in Linux Driver
1.3. Reference Design Walk-through x
1.3.1. System Requirements 1.3.2. Reference Design User Guide
1.3.2. Reference Design User Guide x
1.3.2.1. Hardware Setup 1.3.2.2. Executing The Reference Design 1.3.2.3. Replacing RBF File
1.3.2.1. Hardware Setup x
1.3.2.1.1. Loading the Boot Image into SD Card 1.3.2.1.2. Setting Up Development Kit 1.3.2.1.3. Booting Up The Reference Design
1.4. System Architecture x
1.4.1. System Modules 1.4.2. Clocking and Reset Scheme 1.4.3. System Parameters 1.4.4. System Register Map 1.4.5. Interface Signals
1.4.1. System Modules x
1.4.1.1. MAC 1.4.1.2. Time of Day (ToD) 1.4.1.3. Packet Parser 1.4.1.4. The Central Processing Unit (CPU) 1.4.1.5. FIFO
1.4.4. System Register Map x
1.4.4.1. MAC Registers 1.4.4.2. Transceiver Registers 1.4.4.3. PTP Control Registers 1.4.4.4. 1588 ToD Clock Registers
1.4.5. Interface Signals x
1.4.5.1. Clock and Reset Signals 1.4.5.2. PHY Interface Signals 1.4.5.3. HPS Signals
1. Altera 1588 System Solution

1.4.3. System Parameters

This section describes the parameters used for the modules used in the reference design that are instantiated from the Quartus II software IP catalog.
The following table shows the parameter settings in the Altera 10G-bps Ethernet MAC IP for this reference design. Altera recommends keeping the specified parameter settings as set in the project when using the reference design.
Table 1.  Parameters Settings for Altera 10G-bps Ethernet MAC IP
Parameter Setting
Speed 10 Gbps
Datapath option: TX & RX
Enable preamble pass-through mode Turn off
Enable priority-based flow control (PFC) Turn off
Enable supplementary address Turn off
Enable CRC on transmit path Turn on
Enable statistics collection Turn on
Statistics counters: Memory-based
Enable time stamping Turn on
Enable PTP one-step clock support Turn on
The following table shows the parameter settings in the Altera 10GBASE-R PHY IP for this reference design. Altera recommends keeping the specified parameter settings as set in the project when using the reference design.
Table 2.  Parameters Settings for Altera 10GBASE-R PHY IP
Parameter Setting
Number of channels: 1
Mode of operation: duplex
PLL type: CMU
Reference clock frequency: 644.53125 MHz
Enable additional control and status pins Turn off
Enable rx_recovered_clk_pin Turn off
Enable pll_locked_status port Turn off
Enable rx_coreclkin_port Turn off
Enable embedded reset controller Turn on
Enable IEEE 1588 latency adjustment ports Turn on
The following table shows the parameter settings in the Altera Transceiver Reconfiguration Controller IP for this reference design. Altera recommends keeping the specified parameter settings as set in the project when using the reference design.
Table 3.  Parameters Settings for Altera Transceiver Reconfiguration Controller IP
Parameter Setting
Number of reconfiguration interfaces: 2
Optional interface grouping: Leave blank
Enable offset cancellation Turn on by default
Enable duty cycle calibration Turn off
Create optional calibration status ports Turn off
Enable Analog controls Turn on
Enable channel/PLL reconfiguration Turn off
Enable PLL reconfiguration support block Turn off
The following table shows the parameter settings in the Altera Ethernet IEEE 1588 Time of Day Clock IP for this reference design. Altera recommend keeping the specified parameter settings as set in the project when using the reference design.
Table 4.  Parameters Settings for Altera Ethernet IEEE 1588 Time of Day Clock IP
Parameter Setting
DEFAULT_NSEC_PERIOD: 6
DEFAULT_FNSEC_PERIOD: 0x00006666
DEFAULT_NSEC_ADJPERIOD: 6
DEFAULT_FNSEC_ADJPERIOD: 0x00006666
Related Information
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