AN 739: Altera 1588 System Solution

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ID 683410
Date 1/28/2016
Public
Document Table of Contents
Document Table of Contents x
1. Altera 1588 System Solution
1. Altera 1588 System Solution x
1.1. Altera 1588 System Level Overview 1.2. Precision Time Protocol (PTP) Concept in A 1588 System 1.3. Reference Design Walk-through 1.4. System Architecture 1.5. Altera 1588 System Solution Document Revision History
1.2. Precision Time Protocol (PTP) Concept in A 1588 System x
1.2.1. Understanding the Different PTP Clocks 1.2.2. Precision Time Protocol (PTP) Synchronization Process 1.2.3. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System 1.2.4. Functional Flow For A 1588 Transparent Clock Master/Slave Mode System 1.2.5. Functional Flow for A 1588 Boundary Clock Mode System 1.2.6. Timestamp Packet Functional Flow in Linux Driver
1.3. Reference Design Walk-through x
1.3.1. System Requirements 1.3.2. Reference Design User Guide
1.3.2. Reference Design User Guide x
1.3.2.1. Hardware Setup 1.3.2.2. Executing The Reference Design 1.3.2.3. Replacing RBF File
1.3.2.1. Hardware Setup x
1.3.2.1.1. Loading the Boot Image into SD Card 1.3.2.1.2. Setting Up Development Kit 1.3.2.1.3. Booting Up The Reference Design
1.4. System Architecture x
1.4.1. System Modules 1.4.2. Clocking and Reset Scheme 1.4.3. System Parameters 1.4.4. System Register Map 1.4.5. Interface Signals
1.4.1. System Modules x
1.4.1.1. MAC 1.4.1.2. Time of Day (ToD) 1.4.1.3. Packet Parser 1.4.1.4. The Central Processing Unit (CPU) 1.4.1.5. FIFO
1.4.4. System Register Map x
1.4.4.1. MAC Registers 1.4.4.2. Transceiver Registers 1.4.4.3. PTP Control Registers 1.4.4.4. 1588 ToD Clock Registers
1.4.5. Interface Signals x
1.4.5.1. Clock and Reset Signals 1.4.5.2. PHY Interface Signals 1.4.5.3. HPS Signals
1. Altera 1588 System Solution

1.2.2. Precision Time Protocol (PTP) Synchronization Process

The synchronization process involves ToD (Time of Day) offset correction and frequency correction between a master clock and a slave clock. The slave clock collects necessary data to synchronize its clock with master’s clock through event messages. Below is the synchronization process flow:

  1. The slave collects the timestamps of T1, T2, T3 and T4 through the event messages; Sync, Delay_Req, and Delay_Resp and calculates the mean path delay (MPD).
  2. At the next sync message, the slave calculates the ToD offset by subtracting the MPD from the result of T6-T5 and adjusts its ToD counter accordingly.
  3. Next, the slave clock calculates the frequency offset by comparing the time difference in frequency between 2 successively transmitted and received sync messages per the following equation:

    Frequency offset = (Fo - Fr)/Fr

    where Fo = 1/(T5-T1) and Fr = 1/(T6-T2),

    T1 = Initial time for first transmitted sync message from master clock
    T2 = Initial time for first received sync message from slave clock
    T5 = Initial time for second transmitted sync message from master clock
    T6 = Initial time for second received sync message from slave clock

  4. The slave clock calculates ToD offset and frequency offset continuously to maintain its ToD counter corresponding to the master clock to the best possible accuracy. This is most often accomplished through frequent syntonization offset adjustments after the initial ToD offset adjustment and occasional ToD offset adjustments.
Figure 3. Synchronization Between Master and Slave Clocks

The function of TC nodes is to calculate the residence delays of the PTP packets between a master clock and a slave clock to provide a more accurate offset. However, a long chain of TC nodes increases inaccuracy in synchronization.

Figure 4. Synchronization Between Master and Slave Clocks with Transparent Clock Mode

The BC device is used to break the long chain of TC nodes and maintain the accuracy of the synchronization. The BC device has a slave clock port synchronizing to a master clock external to the BC system. The master ports in a BC system use the timescale maintained by the slave clock within the same BC system.

Altera Ethernet MAC and transceiver IPs with fractional arithmetic capability can provide highest accuracy of 6.99ns for Ethernet link of 10Gbps speed, facilitating synchronization required even for stringent applications such as telecom and mobile backhaul. Further, the design facilitates visual demonstration of the achieved synchronization through PPS (pulse per second) output. The efficacy of the synchronization between the master and slave clock can be observe through the PPS output in an oscilloscope.

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