AN 739: Altera 1588 System Solution

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ID 683410
Date 1/28/2016
Public
Document Table of Contents
Document Table of Contents x
1. Altera 1588 System Solution
1. Altera 1588 System Solution x
1.1. Altera 1588 System Level Overview 1.2. Precision Time Protocol (PTP) Concept in A 1588 System 1.3. Reference Design Walk-through 1.4. System Architecture 1.5. Altera 1588 System Solution Document Revision History
1.2. Precision Time Protocol (PTP) Concept in A 1588 System x
1.2.1. Understanding the Different PTP Clocks 1.2.2. Precision Time Protocol (PTP) Synchronization Process 1.2.3. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System 1.2.4. Functional Flow For A 1588 Transparent Clock Master/Slave Mode System 1.2.5. Functional Flow for A 1588 Boundary Clock Mode System 1.2.6. Timestamp Packet Functional Flow in Linux Driver
1.3. Reference Design Walk-through x
1.3.1. System Requirements 1.3.2. Reference Design User Guide
1.3.2. Reference Design User Guide x
1.3.2.1. Hardware Setup 1.3.2.2. Executing The Reference Design 1.3.2.3. Replacing RBF File
1.3.2.1. Hardware Setup x
1.3.2.1.1. Loading the Boot Image into SD Card 1.3.2.1.2. Setting Up Development Kit 1.3.2.1.3. Booting Up The Reference Design
1.4. System Architecture x
1.4.1. System Modules 1.4.2. Clocking and Reset Scheme 1.4.3. System Parameters 1.4.4. System Register Map 1.4.5. Interface Signals
1.4.1. System Modules x
1.4.1.1. MAC 1.4.1.2. Time of Day (ToD) 1.4.1.3. Packet Parser 1.4.1.4. The Central Processing Unit (CPU) 1.4.1.5. FIFO
1.4.4. System Register Map x
1.4.4.1. MAC Registers 1.4.4.2. Transceiver Registers 1.4.4.3. PTP Control Registers 1.4.4.4. 1588 ToD Clock Registers
1.4.5. Interface Signals x
1.4.5.1. Clock and Reset Signals 1.4.5.2. PHY Interface Signals 1.4.5.3. HPS Signals
1. Altera 1588 System Solution

1.3.2.3. Replacing RBF File

At times, you may need to modify the reference design according to your system requirements and recompile the reference design. You are required to regenerate the altera_eth_10g_1588_ref_design_msgdma_top.qsys file for compilation. Following are the steps to guide you in regenerating the design files and replacing the RBF file into the system image. You are required to use Quartus II Subscription Edition v14.1 for these procedures.

  1. Download the alt_eth_1588_rd.qsys.zip file to your computer and unzip the folder.
  2. Launch Quartus II software. In Quartus II software, click File -> Open Project and browse to av_1588_top.qpf file to open the reference design project.
  3. Once the the project file is open, click on Tools -> Qsys in the Quartus II software.
  4. In the Qsys interface, click File -> Open and browse to altera_eth_10g_1588_ref_design_msgdma_top.qsys file to open the reference design Qsys file.
  5. Once the reference design Qsys file is opened, click Generate HDL.
    Figure 19. Generating HDL File in Qsys
  6. You will see the Generation dialog box appear. You may choose Verilog or VHDL for synthesis file type.
  7. Browse to the location where you want to store the generated output files under the Output Directory and click Generate. Click Close once the files generation completed.
    Figure 20. Generation Dialog Box
  8. In Quartus II software, click Processing -> Start Compilation to recompile the reference design. You will see av_1588_top.sof file in the output_files folder once compilation is completed.
  9. Create a new text file titled option.txt with the following content.
    bitstream_compression=on
  10. At the command prompt in Linux or DOS, type quartus_cpf -o <project_dir>/option.txt -c av_1588_top.sof soc_system.rbf to generate the .rbf (file name tag) file.
  11. You can replace the soc_system.rbf file in the SD card with the newly generated RBF file.
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