AN 739: Altera 1588 System Solution

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ID 683410
Date 1/28/2016
Public
Document Table of Contents
Document Table of Contents x
1. Altera 1588 System Solution
1. Altera 1588 System Solution x
1.1. Altera 1588 System Level Overview 1.2. Precision Time Protocol (PTP) Concept in A 1588 System 1.3. Reference Design Walk-through 1.4. System Architecture 1.5. Altera 1588 System Solution Document Revision History
1.2. Precision Time Protocol (PTP) Concept in A 1588 System x
1.2.1. Understanding the Different PTP Clocks 1.2.2. Precision Time Protocol (PTP) Synchronization Process 1.2.3. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System 1.2.4. Functional Flow For A 1588 Transparent Clock Master/Slave Mode System 1.2.5. Functional Flow for A 1588 Boundary Clock Mode System 1.2.6. Timestamp Packet Functional Flow in Linux Driver
1.3. Reference Design Walk-through x
1.3.1. System Requirements 1.3.2. Reference Design User Guide
1.3.2. Reference Design User Guide x
1.3.2.1. Hardware Setup 1.3.2.2. Executing The Reference Design 1.3.2.3. Replacing RBF File
1.3.2.1. Hardware Setup x
1.3.2.1.1. Loading the Boot Image into SD Card 1.3.2.1.2. Setting Up Development Kit 1.3.2.1.3. Booting Up The Reference Design
1.4. System Architecture x
1.4.1. System Modules 1.4.2. Clocking and Reset Scheme 1.4.3. System Parameters 1.4.4. System Register Map 1.4.5. Interface Signals
1.4.1. System Modules x
1.4.1.1. MAC 1.4.1.2. Time of Day (ToD) 1.4.1.3. Packet Parser 1.4.1.4. The Central Processing Unit (CPU) 1.4.1.5. FIFO
1.4.4. System Register Map x
1.4.4.1. MAC Registers 1.4.4.2. Transceiver Registers 1.4.4.3. PTP Control Registers 1.4.4.4. 1588 ToD Clock Registers
1.4.5. Interface Signals x
1.4.5.1. Clock and Reset Signals 1.4.5.2. PHY Interface Signals 1.4.5.3. HPS Signals
1. Altera 1588 System Solution

1.4.5.3. HPS Signals

Table 14.  Arria V HPS Interface Signals
Signal Direction Width Description
HPS DDR3 SDRAM 
hps_memory_mem_a
 Output 15 Address bus. 
hps_memory_mem_ba
 Output 3 Bank address. 
hps_memory_mem_ck
mem_ck_n
 Output 1 Memory clock. 
mem_cke
Output 1

Clock enable. 

mem_cs_n
Output 1

Chip select.. 

mem_ras_n
Output 1

Row address strobe. 

mem_cas_n
Output 1

Column address strobe. 

mem_we_n
Output 1

Write enable. 

mem_reset_n
Output 1

Reset 

mem_dq
Bidirectional 40

Data. 

mem_dqs
Bidirectional 5

Data strobe. 

mem_dqs_n
 Bidirectional 5

Data strobe. 

mem_odt
Output 1

On-die termination. 

mem_dm
Output 5

Data mask.

oct_rzqin Input 1 OCT reference resistor pins for RZQ.
HPS Peripheral 
hps_uart0_TX
 Output 1 Output signal for UART channel 0.

This signal is required for serial console communication to host. 

hps_uart0_RX
 Input 1 Input signal for UART channel 0.

This signal is required for serial console communication to host.

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