AN 739: Altera 1588 System Solution

Download PDF
ID 683410
Date 1/28/2016
Public
Document Table of Contents
Document Table of Contents x
1. Altera 1588 System Solution
1. Altera 1588 System Solution x
1.1. Altera 1588 System Level Overview 1.2. Precision Time Protocol (PTP) Concept in A 1588 System 1.3. Reference Design Walk-through 1.4. System Architecture 1.5. Altera 1588 System Solution Document Revision History
1.2. Precision Time Protocol (PTP) Concept in A 1588 System x
1.2.1. Understanding the Different PTP Clocks 1.2.2. Precision Time Protocol (PTP) Synchronization Process 1.2.3. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System 1.2.4. Functional Flow For A 1588 Transparent Clock Master/Slave Mode System 1.2.5. Functional Flow for A 1588 Boundary Clock Mode System 1.2.6. Timestamp Packet Functional Flow in Linux Driver
1.3. Reference Design Walk-through x
1.3.1. System Requirements 1.3.2. Reference Design User Guide
1.3.2. Reference Design User Guide x
1.3.2.1. Hardware Setup 1.3.2.2. Executing The Reference Design 1.3.2.3. Replacing RBF File
1.3.2.1. Hardware Setup x
1.3.2.1.1. Loading the Boot Image into SD Card 1.3.2.1.2. Setting Up Development Kit 1.3.2.1.3. Booting Up The Reference Design
1.4. System Architecture x
1.4.1. System Modules 1.4.2. Clocking and Reset Scheme 1.4.3. System Parameters 1.4.4. System Register Map 1.4.5. Interface Signals
1.4.1. System Modules x
1.4.1.1. MAC 1.4.1.2. Time of Day (ToD) 1.4.1.3. Packet Parser 1.4.1.4. The Central Processing Unit (CPU) 1.4.1.5. FIFO
1.4.4. System Register Map x
1.4.4.1. MAC Registers 1.4.4.2. Transceiver Registers 1.4.4.3. PTP Control Registers 1.4.4.4. 1588 ToD Clock Registers
1.4.5. Interface Signals x
1.4.5.1. Clock and Reset Signals 1.4.5.2. PHY Interface Signals 1.4.5.3. HPS Signals
1. Altera 1588 System Solution

1.2.5. Functional Flow for A 1588 Boundary Clock Mode System

The function of a boundary clock mode system is to terminate a long chain of transparent clocks leading to high inaccuracy, and maintain a single timescale. A boundary clock commonly contains a slave clock port and at least one master clock port. However, the boundary clock has all the ports in one domain and maintain the timescale used in the domain.

The following figure illustrates a BC mode system consists of one slave port and two master ports. The BC-slave port synchronizes with an external grand master clock through the network. The BC-master ports synchronizes its clocks with the BC-slave port. In the figure, one ToD module is connected to the BC-slave port and the BC-master ports. Each of the ports shown in the figure operates independently. Timestamp T1 and T2 are synchronized to an external grand master clock while timestamp T3 and T4 are synchronizes to the BC-slave ToD. The CPU hosts the independent stacks for the BC-slave port and the two BC-master ports with the common timescale of the BC-slave ToD.

Figure 8. Functional Flow For 1588 Boundary Clock in Master & Slave Mode
Timestamp Functional Flow for BC Slave Port:
  1. The receiving MAC of the BC-slave port receives a Sync packet with timestamp T1 from external 1588 system through cable A and generates timestamp T2.
  2. A packet parser validates the incoming packet and stores timestamp T2 and its fingerprint in the FIFO.
  3. The CPU receives the Sync packet with timestamp T1 via user logic. 3
  4. In 2-step mechanism, the receiving MAC of BC-slave port receives a Follow-Up message timestamp T1 which refers to the Sync message in step 1.
  5. The CPU then reads the FIFO to collect the fingerprint and the timestamp T2.
  6. The CPU sends Delay_Req packet via its user logic..
  7. The packet parser block after decoding the PTP packet extracts the fingerprint and sends it to the MAC block along with the packet.
  8. The MAC Tx of the BC-slave generates timestamp T3 before sending the packet to the PHY and stores the timestamp along with its fingerprint in the FIFO.
  9. The CPU then reads the FIFO and collects fingerprint and timestamp T3.
  10. The receiving MAC receives a Delay_Response packet and timestamp the packet. The MAC then stores the timestamp in the FIFO and forward the Delay_Response packet to packet parser
  11. The packet parser validates the packet and extracts the fingerprint before storing it in the FIFO.
  12. The CPU receives the Delay_Response packet with timestamp T4. The CPU then reads the FIFO but the timestamp collected through the FIFO read is ignored by the software stack. .
Timestamp Functional Flow for BC Master Port:
  1. The CPU sends a Sync packet to the external 1588 system through MAC Tx and the PHY.
  2. The packet parser block extracts the fingerprint after decoding the Sync packet and sends the fingerprint to the MAC Tx along with the packet.
  3. The MAC Tx generates timestamp T5 for the Sync packet before sending it to the PHY.3 The MAC Tx then stores the timestamp T5 with its fingerprint in the FIFO.
  4. The CPU then reads the FIFO to collect the fingerprint and the timestamp T5.
  5. For 2-step mechanism, the CPU sends a Follow-up message with timestamp T5 referring to the Sync packet sent in step 1.
  6. The receiving MAC of the BC-master clock receives a PDelay_Req from external 1588 system through the PHY.
  7. The MAC Rx receives the PDelay_Req packet and generates timestamp T6 before storing it in the FIFO. It then sends the PDelay_Req to the packet parser.
  8. The packet parser decodes the packet and extracts its fingerprint before storing in the FIFO.
  9. The CPU receives the PDelay_Req packet via user logic and collects the fingerprint and the timestamp T6 from the FIFO.
  10. The CPU sends a PDelay_Resp packet containing the timestamp T6 to the packet parser.
  11. The packet parser validates and extracts the PDelay_Resp packet fingerprint before sending it to the MAC.3
  12. The MAC Tx receives the packet and generates a timestamp before storing the timestamp and its fingerprint into the FIFO for CPU to read. However, this timestamp is ignore by the software stack. The MAC Tx then sends the PDelay_Resp packet as it is.
  13. For 2-step mechanism, the CPU reads the entry from the FIFO to collect the timestamp T6 and its fingerprint
  14. The CPU then sends a Pdelay_Resp_Follow_Up packet with timestamp T6 to the external 1588 system.
3 This flow is only applicable in a 1-step mechanism.
Level Two Title