AN 739: Altera 1588 System Solution

Download PDF
ID 683410
Date 1/28/2016
Public
Document Table of Contents
Document Table of Contents x
1. Altera 1588 System Solution
1. Altera 1588 System Solution x
1.1. Altera 1588 System Level Overview 1.2. Precision Time Protocol (PTP) Concept in A 1588 System 1.3. Reference Design Walk-through 1.4. System Architecture 1.5. Altera 1588 System Solution Document Revision History
1.2. Precision Time Protocol (PTP) Concept in A 1588 System x
1.2.1. Understanding the Different PTP Clocks 1.2.2. Precision Time Protocol (PTP) Synchronization Process 1.2.3. Functional Flow For A 1588 Ordinary Clock Master/Slave Mode System 1.2.4. Functional Flow For A 1588 Transparent Clock Master/Slave Mode System 1.2.5. Functional Flow for A 1588 Boundary Clock Mode System 1.2.6. Timestamp Packet Functional Flow in Linux Driver
1.3. Reference Design Walk-through x
1.3.1. System Requirements 1.3.2. Reference Design User Guide
1.3.2. Reference Design User Guide x
1.3.2.1. Hardware Setup 1.3.2.2. Executing The Reference Design 1.3.2.3. Replacing RBF File
1.3.2.1. Hardware Setup x
1.3.2.1.1. Loading the Boot Image into SD Card 1.3.2.1.2. Setting Up Development Kit 1.3.2.1.3. Booting Up The Reference Design
1.4. System Architecture x
1.4.1. System Modules 1.4.2. Clocking and Reset Scheme 1.4.3. System Parameters 1.4.4. System Register Map 1.4.5. Interface Signals
1.4.1. System Modules x
1.4.1.1. MAC 1.4.1.2. Time of Day (ToD) 1.4.1.3. Packet Parser 1.4.1.4. The Central Processing Unit (CPU) 1.4.1.5. FIFO
1.4.4. System Register Map x
1.4.4.1. MAC Registers 1.4.4.2. Transceiver Registers 1.4.4.3. PTP Control Registers 1.4.4.4. 1588 ToD Clock Registers
1.4.5. Interface Signals x
1.4.5.1. Clock and Reset Signals 1.4.5.2. PHY Interface Signals 1.4.5.3. HPS Signals
1. Altera 1588 System Solution

1.1. Altera 1588 System Level Overview

IEEE 1588v2 is a standard that defines a Precision Time Protocol (PTP) used in packet networking to precisely synchronize the real Time-of-Day (ToD) clocks and frequency sources in a distributed system to a master ToD clock, which is synchronized to a global clock source. Traditionally, such synchronization has been achieved in TDM (Time Division Multiplexing) networks due to their control on timing with their precise frequency and clocking hierarchy. However, with the advent of 1588v2, synchronization to nanosecond precision has become a possibility within packet networks, enabling low-cost phase and frequency synchronization in applications such as wireless, mobile backhaul, wireline and industrial instrumentation potentially replacing the higher cost of TDM networks.

The following diagram illustrates the 1588 system solution using Altera developed Ethernet driver and PTP stack running on top of Altera SoC, Ethernet MAC and transceiver with 1588 capability IPs. The software stack also provides accessibility to control and status registers for configuration using Ethtool and accessibility to the MAC statistic counters to observe the system performance using iperf utility.

Though the complete solution can be implemented in software, the hardware assisted the system to achieve the high accuracy needed in some applications such as mobile backhaul. All Altera Ethernet MAC and PHY 1588 hardware solution supports a static error of +/- 3ns for throughputs of 10Gbps with random error of +/- 1ns from the PHY.

Figure 1. 1588 System Solution Using Altera Ethernet MAC And PHY Hardware IP
Level Two Title