F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683372
Date 12/17/2021
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Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Programmed Input/Output Design Example Functional Description 2.3. Programmed Input/Output Design Example Simulation Testbench 2.4. Single Root I/O Virtualization (SR-IOV) Design Example 2.5. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description 2.6. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench
2.2. Programmed Input/Output Design Example Functional Description x
2.2.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.2. PIO Application (APPS) 2.2.3. On-Chip Memory (MEM) 2.2.4. F-Tile Reference and System PLL Clocks IP 2.2.5. Reset Release IP
2.2.2. PIO Application (APPS) x
2.2.2.1. Scheduler 2.2.2.2. Read Write Module 2.2.2.3. Avalon-MM Interface 2.2.2.4. Completion Module 2.2.2.5. Width Adapter
2.5. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description x
2.5.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.5.2. SR-IOV Applications (APPS)
2.5.2. SR-IOV Applications (APPS) x
2.5.2.1. Access Parser 2.5.2.2. Access Router 2.5.2.3. Completion 2.5.2.4. PF Segram 2.5.2.5. VF Segram 2.5.2.6. F-Tile Reference and System PLL Clocks IP 2.5.2.7. Reset Release IP
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Installing the Linux Kernel Driver 3.6. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. Testbench
3.3.1. Testbench x
3.3.1.1. Test Driver Module 3.3.1.2. PIO Design Example Testbench 3.3.1.3. SR-IOV Design Example Testbench
3.6. Running the Design Example x
3.6.1. Running the PIO Design Example 3.6.2. Running the SR-IOV Design Example
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

2.4. Single Root I/O Virtualization (SR-IOV) Design Example

Figure 10. PCIe Gen 4 x16 Single Root I/O Virtualization (SR-IOV) Design Example Block Diagram

The SR-IOV design example performs memory transfers from a host processor to a target Intel Agilex device configured as Gen4 x16 Endpoint. The design example runs up to 500 MHz at user interface with the maximum data width interface of 512 bits. It demonstrates the SR-IOV capability of 2 PF and up to 32 VF per PF. With two PFs and 32 VFs per PF, there are 66 memory locations that the design example can access. The two PFs can access two memory locations, while the 64 VFs (2 x 32) can access 64 memory locations.

The design example is intended to handle simple read/write instructions based on TLP command. TLP transaction of memory write request (MWr) writes the data to the designated RAM memory space. As for the TLP transaction of memory read request (MRd), the design reads the data from RAM memory space and returns completion with data (CplD). The data and address requested to access the SR-IOV APPS must be double word aligned.

The SR-IOV design example automatically creates the files necessary to simulate and compile in the Intel® Quartus® Prime software. The design example covers a wide range of parameters. However, it does not cover all possible parameterizations of the F-Tile Hard IP for PCIe.

This design example consists of 2 main components:
  • F-Tile Avalon-ST IP for PCI Express Hard IP Endpoint variant (DUT)
  • The SR-IOV Application (APPS)
Level Two Title