F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683372
Date 12/17/2021
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Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Programmed Input/Output Design Example Functional Description 2.3. Programmed Input/Output Design Example Simulation Testbench 2.4. Single Root I/O Virtualization (SR-IOV) Design Example 2.5. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description 2.6. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench
2.2. Programmed Input/Output Design Example Functional Description x
2.2.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.2. PIO Application (APPS) 2.2.3. On-Chip Memory (MEM) 2.2.4. F-Tile Reference and System PLL Clocks IP 2.2.5. Reset Release IP
2.2.2. PIO Application (APPS) x
2.2.2.1. Scheduler 2.2.2.2. Read Write Module 2.2.2.3. Avalon-MM Interface 2.2.2.4. Completion Module 2.2.2.5. Width Adapter
2.5. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description x
2.5.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.5.2. SR-IOV Applications (APPS)
2.5.2. SR-IOV Applications (APPS) x
2.5.2.1. Access Parser 2.5.2.2. Access Router 2.5.2.3. Completion 2.5.2.4. PF Segram 2.5.2.5. VF Segram 2.5.2.6. F-Tile Reference and System PLL Clocks IP 2.5.2.7. Reset Release IP
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Installing the Linux Kernel Driver 3.6. Running the Design Example
3.3. Simulating the Design Example x
Generating tile files 3.3.1. Testbench
3.3.1. Testbench x
3.3.1.1. Test Driver Module 3.3.1.2. PIO Design Example Testbench 3.3.1.3. SR-IOV Design Example Testbench
3.6. Running the Design Example x
3.6.1. Running the PIO Design Example 3.6.2. Running the SR-IOV Design Example
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

3.3. Simulating the Design Example

Generating tile files

The tile files are generated during the design example generation. Runnning Support-Logic Generation manually is not required before simulating the design example.

Tile files generation is a required step before simulation if you created your design with the F-Tile Avalon-ST IP for PCI Express from scratch. You can run Analysis & Elaboration on the Processing menu in the Intel® Quartus® Prime Pro Edition software to generate the F-Tile specific tiles file for your design. The Support-Logic Generation command runs automatically as part of the process.

A successful tile file generation results in the <IP_instance_name>__tiles.x files where x represents the necessary file extensions. The generated files are located in your project directory and contain the full netlist for simulation and synthesis.

Figure 17. Procedure
  1. Run the simulation script under <example_design>/pcie_ed_tb/pcie_ed_tb/sim/<simulator> directory for the simulator of your choice. Refer to the table below.
  2. Analyze the results.
Note: F-Tile does not support parallel PIPE simulations.
Table 3.  Steps to Run Simulation
Simulator Working Directory Instructions
VCS* <example_design>/pcie_ed_tb/pcie_ed_tb/sim/synopsys/vcs/
  1. Type 
    sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="+vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ +define+RTLSIM\ +define+SSM_SEQUENCE\" USER_DEFINED_SIM_OPTIONS="" | tee simulation.log
    Note: The command above is a single-line command.
  2. A successful simulation ends with the following message, 
    "Simulation stopped due to successful completion!"
    in the simulation.log file that was generated.
Note: To run a simulation in interactive mode, use the following steps: (if you already generated a simv executable in noninteractive mode, delete the simv and simv.diadir)
  1. Open the vcs_setup.sh file and add a debug option to the VCS command: 
    vcs -debug_access+all
  2. Compile the design example: 
    sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="+vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ +define+RTLSIM\ +define+SSM_SEQUENCE\  " SKIP_SIM=1
  3. Start the simulation in interactive mode: 
    simv -gui &

VCSMX

 <example_design>/pcie_ed_tb/pcie_ed_tb/sim/synopsys/vcsmx/
  1. Type 
    sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="+define+RTLSIM\ +define+SSM_SEQUENCE\ -sverilog\ +define+QUARTUS_ENABLE_DPI_FORCE\ " USER_DEFINED_ELAB_OPTIONS="\$QUARTUS_INSTALL_DIR/eda/sim_lib/quartus_dpi.c\ -debug_access+f\ +vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ " USER_DEFINED_SIM_OPTIONS="" | tee simulation.log
    Note: The command above is a single-line command.
  2. A successful simulation ends with the following message, 
    "Simulation stopped due to successful completion!"
    in the simulation.log file that was generated.
Note: To run a simulation in interactive mode, use the following steps: (if you already generated a simv executable in noninteractive mode, delete the simv and simv.diadir)
  1. Open the vcsmx_setup.sh file and add a debug option to the VCS command: 
    vcs -debug_access+all
  2. Compile the design example: 
    sh vcsmx_setup.sh USER_DEFINED_ELAB_OPTIONS="+vcs+lic+wait\ -full64\ -hsopt=gates\ -debug_pp\ +define+RTLSIM\ +define+SSM_SEQUENCE\  " SKIP_SIM=1
  3. Start the simulation in interactive mode: 
    simv -gui &

QuestaSim*

ModelSim* SE

Questa*-Intel FPGA Edition

<example_design>/ pcie_ed_tb/pcie_ed_tb/sim/mentor/

  1. Invoke vsim (by typing vsim, which brings up a console window where you can run the following commands).
  2. do msim_setup.tcl
  3. ld_debug
  4. run -all
  5. A successful simulation ends with the following message: 
    "Simulation stopped due to successful completion!"

Xcelium

<example_design>/ pcie_ed_tb/pcie_ed_tb/sim/xcelium/

  1. Type 
    sh xcelium_setup.sh USER_DEFINED_VERILOG_COMPILE_OPTIONS="+define+RTLSIM\ +define+SSM_SEQUENCE\ -sv\" USER_DEFINED_ELAB_OPTIONS="-timescale\ 1ns/1ps" USER_DEFINED_SIM_OPTIONS="-input\ @run" | tee simulation.log
    Note: The command above is a single-line command.
  2. A successful simulation ends with the following message in the simulation.log file that was generated. 
    "Simulation stopped due to successful completion!"

The simulation reports, "Simulation stopped due to successful completion" if no errors occur.

The same procedure applicable for PCIe Gen3/4 x16, PCIe Gen3/4 x8x8 and PCIe Gen3/4 x8 design example variants.

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