F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683372
Date 12/17/2021
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Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Programmed Input/Output Design Example Functional Description 2.3. Programmed Input/Output Design Example Simulation Testbench 2.4. Single Root I/O Virtualization (SR-IOV) Design Example 2.5. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description 2.6. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench
2.2. Programmed Input/Output Design Example Functional Description x
2.2.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.2. PIO Application (APPS) 2.2.3. On-Chip Memory (MEM) 2.2.4. F-Tile Reference and System PLL Clocks IP 2.2.5. Reset Release IP
2.2.2. PIO Application (APPS) x
2.2.2.1. Scheduler 2.2.2.2. Read Write Module 2.2.2.3. Avalon-MM Interface 2.2.2.4. Completion Module 2.2.2.5. Width Adapter
2.5. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description x
2.5.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.5.2. SR-IOV Applications (APPS)
2.5.2. SR-IOV Applications (APPS) x
2.5.2.1. Access Parser 2.5.2.2. Access Router 2.5.2.3. Completion 2.5.2.4. PF Segram 2.5.2.5. VF Segram 2.5.2.6. F-Tile Reference and System PLL Clocks IP 2.5.2.7. Reset Release IP
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Installing the Linux Kernel Driver 3.6. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. Testbench
3.3.1. Testbench x
3.3.1.1. Test Driver Module 3.3.1.2. PIO Design Example Testbench 3.3.1.3. SR-IOV Design Example Testbench
3.6. Running the Design Example x
3.6.1. Running the PIO Design Example 3.6.2. Running the SR-IOV Design Example
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

3.5. Installing the Linux Kernel Driver

Before you can test the design example in hardware, you must install the Linux kernel driver. You can use this driver to perform the following tests:
  • A PCIe link test that performs 100 writes and reads
  • Memory space DWORD(1) reads and writes
  • Configuration Space DWORD reads and writes
Note: Throughout this user guide, the term word DWORD has the same meaning as in the PCI Express Base Specification. A word is 16 bits and a DWORD is 32 bits.
In addition, you can use the driver to change the value of the following parameters:
  • The BAR being used
  • The selected device (by specifying the bus, device and function (BDF) numbers for the device)

Complete the following steps to install the kernel driver

  1. Navigate to ./software/kernel/linux under the example design generation directory.
  2. Change the permissions on the install, load, and unload files
    $ chmod 777 install load unload
  3. Install the driver
    $ sudo ./install
  4. Verify the driver installation
    $ lsmod | grep intel_fpga_pcie_drv
    Expected Result 
    intel_fpga_pcie_drv 17792 0
  5. Verify that Linux recognizes the PCIe design example
    $ lspci -d 1172:000 -v | grep intel_fpga_pcie_drv
    Expected result. Kernel driver in use: 
    intel_fpga_pcie_drv
    Note: If you have changed the Vendor ID, substitute the new Vendor ID for Intel's Vendor ID in this command.
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