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2.1. Programmed Input/Output Design Example
2.2. Programmed Input/Output Design Example Functional Description
2.3. Programmed Input/Output Design Example Simulation Testbench
2.4. Single Root I/O Virtualization (SR-IOV) Design Example
2.5. Single Root I/O Virtualization (SR-IOV) Design Example Functional Description
2.6. Single Root I/O Virtualization (SR-IOV) Design Example Simulation Testbench
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Ixiasoft
2.5.2.3. Completion
The Completion submodule stores the necessary header information from the incoming MRd instruction and repackages the acquired information into a CplD header. The CplD header is released together with the fetched data from targeted Segram.