Serial Lite III Streaming Intel® FPGA IP User Guide

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ID 683330
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference 2. About the Serial Lite III Streaming Intel® FPGA IP 3. Getting Started 4. Serial Lite III Streaming IP Core Design Examples 5. Serial Lite III Streaming Intel® FPGA IP Functional Description 6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines 7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers 8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines 9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
2. About the Serial Lite III Streaming Intel® FPGA IP x
2.1. Serial Lite III Streaming Intel® FPGA IP Protocol 2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes 2.3. Performance and Resource Utilization
2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes x
2.2.1. Continuous Mode 2.2.2. Burst Mode
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Intel® FPGA IP Evaluation Mode 3.3. Specifying IP Core Parameters and Options 3.4. Serial Lite III Streaming Intel® FPGA IP Parameters 3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs 3.6. IP Generation Output ( Quartus® Prime Pro Edition) 3.7. IP Core Generation Output ( Quartus® Prime Standard Edition) 3.8. Simulating
3.2. Intel® FPGA IP Evaluation Mode x
3.2.1. Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying IP Core Parameters and Options x
3.3.1. Serial Lite III Streaming Intel® FPGA IP Parameter Editor 3.3.2. Arria® 10 and Cyclone® 10 GX Designs
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters x
3.4.1. Parameters 3.4.2. Parameter Settings for Stratix® 10 Devices IP Debug and Phy Dynamic Reconfiguration 3.4.3. Parameter Settings for Arria® 10 and Cyclone® 10 GX Devices 3.4.4. Parameter Settings for Stratix V and Arria V GZ Devices
3.8. Simulating x
3.8.1. Simulating Intel® FPGA IP Cores 3.8.2. Simulation Parameters 3.8.3. Simulating and Verifying the Design
4. Serial Lite III Streaming IP Core Design Examples x
4.1. Serial Lite III Streaming IP Core Design Example for Stratix® 10 Devices 4.2. Serial Lite III Streaming IP Core Design Example for Arria® 10 and Cyclone® 10 GX Devices 4.3. Serial Lite III Streaming IP Design Examples for Stratix® V Devices
5. Serial Lite III Streaming Intel® FPGA IP Functional Description x
5.1. IP Architecture 5.2. Transmission Overheads and Lane Rate Calculations 5.3. Reset 5.4. Link-Up Sequence 5.5. Error Detection, Reporting, and Recovering Mechanism 5.6. CRC-32 Error Injection 5.7. FIFO ECC Protection 5.8. User Data Interface Waveforms 5.9. Signals 5.10. Accessing Configuration and Status Registers
5.1. IP Architecture x
5.1.1. Serial Lite III Streaming Source Core 5.1.2. Serial Lite III Streaming Sink Core 5.1.3. Serial Lite III Streaming IP Core Duplex Core 5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode 5.1.5. Stratix® 10, Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations
5.1.1. Serial Lite III Streaming Source Core x
5.1.1.1. Source Application Module 5.1.1.2. Source Adaptation Module 5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode 5.1.1.4. Source Clock Generator
5.1.2. Serial Lite III Streaming Sink Core x
5.1.2.1. Sink Application Module 5.1.2.2. Sink Adaptation Module 5.1.2.3. Lane Alignment Module 5.1.2.4. Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode 5.1.2.5. Sink Clock Generator
5.9. Signals x
5.9.1. Serial Lite III Streaming Intel® FPGA IP Interface Signals 5.9.2. Signals for Stratix® 10 Devices 5.9.3. Signals for Arria® 10 and Cyclone® 10 GX Devices 5.9.4. Signals for Stratix® V and Arria® V GZ Devices
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines x
6.1. Standard Clocking Mode 6.2. Advanced Clocking Mode 6.3. Standard Clocking Mode vs Advanced Clocking Mode 6.4. Clocking Implementation Guidelines 6.5. Core Latency
6.1. Standard Clocking Mode x
6.1.1. Standard Clocking Mode in Serial Lite III Streaming Intel® FPGA IP Core ( Stratix® 10 Devices) 6.1.2. Standard Clocking Mode in Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.2. Advanced Clocking Mode x
6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Stratix® 10 Devices) 6.2.2. Advanced Clocking Mode Structure For Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.4. Clocking Implementation Guidelines x
6.4.1. Choosing TX PLL Type
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers x
7.1. Register Map 7.2. Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines x
8.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging
8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging x
8.2.1. Source Core Link Debugging 8.2.2. Sink Core Link Debugging
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide

3.4.2. Parameter Settings for Stratix® 10 Devices

Table 11.   IP
Parameter Value Default Description
General Design Options

Direction

Source, Sink, Duplex

Duplex

Select the variation of the IP. Supports source, sink, or full duplex transmissions.

Note: Sink or source only variant is not supported when you select E-Tile as the transceiver tile in Quartus® Prime Pro Edition v18.1.

Number of lanes

1–24

6

Specifies the number of lanes (equal to physical transceiver links) that are used to transfer the streaming data.

Meta frame length in words

200–8191

200

Specifies the metaframe length.
Transceiver reference clock frequency <Range supported by the transceiver PLLs>

312.5 MHz

 Supports multiple transceiver reference clock frequencies for flexibility in the oscillator and PLL choices. This transceiver reference clock frequency must match the external PLL reference clock frequency for Stratix® 10 L-tile/H-tile devices.
Note: Transceiver reference clock is limited to 500 MHz when you select E-Tile as the transceiver tile in Quartus® Prime Pro Edition v18.1.
VCCR_GXB and VCCT_GXB supply voltage for the Transceiver

1_1V,

1_0V

1_0V

Select VCCR_GXB and VCCT_GXB supply voltages.

Refer to Stratix® 10 Device Family Pin Connection Guidelines for more information related to these pins.

Note: This parameter is not available when you select E-Tile as the transceiver tile.
Transceiver channel type

GX,

GXT

GX

Select the transceiver channel variant.

Select GXT as the transceiver variant to implement data rate more than 17.4 Gbps.
Note: This parameter is not available when you select E-Tile as the transceiver tile.
Enable M20K ECC support Yes/No No Select to use error correcting code (ECC) protection to strengthen the FIFO buffers from single-event upset (SEU) changes. Enables built-in error correcting code (ECC) support on the M20K embedded block memory for single-error correction, double-adjacent-error correction, and triple-adjacent-error detection.
Transceiver Tile

L-Tile,

H-Tile,

E-Tile

<Depending on the transceiver tile supported in the chosen device. For Stratix® 10 devices which support H-Tile and E-Tile, the default value is H-Tile. Reports the actual transceiver tile. The value changes according to the transceiver create tile chosen in the device.
User Interface
Streaming Mode BASIC, FULL FULL Specifies the streaming mode.
  • BASIC: This is a pure streaming mode where data is sent without burst, sync, empty cycle, and frame delimiter to increase bandwidth.
  • FULL: This mode sends a burst and sync cycle at the start of frame and a burst and empty cycle at the end of frame. Provide a gap of one empty cycle between two data frames.
Required idle cycles between bursts 1, 2 2 Supports two values to optimize for bandwidth efficiency or maintain backward compatibility with existing Serial Lite III Streaming IPs (legacy).
  • 1: Recommended for high bandwidth streaming. The same Burst Gap setting must be set for both source and sink IP core.
  • 2: For backward compatibility with Quartus II version 15.1 and older sink IP core.
Adaptation FIFO partial full threshold 8 - 18 15

Specifies the partial full threshold of the transmit FIFO. ready_tx signal will de-assert when data reaches this level in the FIFO.

Clocking mode

Standard clocking mode,

Advanced clocking mode

Standard clocking mode

Specifies the clocking mode.

Refer to Serial Lite III Streaming Intel FPGA IP Clocking Guidelines for more information.

User input

User clock frequency,

Transceiver data rate

User clock frequency

Select User clock frequency to specify the user clock input and allow the IP to determine the transceiver data rate.

Select Transceiver data rate to specify the desired data rate and allow the IP to determine the user clock frequency.

User clock frequency required

Minimum: 50 MHz

Maximum: Limited by the supported transceiver data rates

177.556818 MHz

Specifies the desired frequency for the user clock input for the transmit (Standard Clocking Mode and Advanced Clocking Mode) and receive user interface (Standard Clocking Mode).

This frequency in turn determines the required transceiver data rate to support the calculated transmit and receive bandwidths.

Transceiver data rate

required user clock frequency * overheads * 64

12.5 Gbps

The effective data rate at the output of the transceivers, incorporating transmission and other overheads.

The parameter editor automatically calculates this value by adding the input data rate with transmission overheads to provide you with a selection of user clock frequency.

Aggregate user bandwidth

number of lanes * required user clock frequency * 64

68.18 Gbps

This value is derived by multiplying the number of lanes and user interface data rate.

IP Debug and Phy Dynamic Reconfiguration

Table 12.  Native Transceiver Phy
Parameter Value Default Description
Dynamic Reconfiguration
Enable dynamic reconfiguration On On Enables the dynamic reconfiguration interface.
Note: This parameter is enabled by default and can not be disabled.
Enable Altera Debug Master Endpoint On/Off Off Enables ADME and Optional Reconfiguration Logic parameters of the L-Tile/H-Tile/E-Tile Transceiver Native PHY Stratix® 10 FPGA IP.
Optional Reconfiguration Logic
Enable capability registers On/Off Off Enables capability registers that provide high level information about the configuration f the transceiver channel.
Set user-defined IP identifier User-defined 0 Sets a user-defined numeric identifier that can be read from the user_identifier offset when the capability registers are enabled.
Note: To set the value, enabled the Enable capability registers parameter.
Enable control and status registers On/Off Off Enables soft registers to read status signals and write control signals on the PHY interface through the embedded debug.
Enable Pseudo Random Binary Sequence (PRBS) soft accumulators On/Off Off Enables soft logic for performing PRBS bit and error accumulation when the hard PRBS generator and checker are used.
Note: This parameter is not available when you select E-Tile as the transceiver tile.

For information about parameters in the PMA Adaptation tab, please refer to the PMA Adaptation topic in the Stratix® 10 E-Tile Transceiver PHY User Guide.

Note: The PMA Adaptation tab is only available in Stratix® 10 with E-tile transceiver devices. You must select E-Tile as the Transceiver Tile to use the parameters in the PMA Adaptation tab.
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