Visible to Intel only — GUID: bhc1460601636782
Ixiasoft
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Intel® FPGA IP Evaluation Mode
3.3. Specifying IP Core Parameters and Options
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters
3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs
3.6. IP Generation Output ( Quartus® Prime Pro Edition)
3.7. IP Core Generation Output ( Quartus® Prime Standard Edition)
3.8. Simulating
5.1. IP Architecture
5.2. Transmission Overheads and Lane Rate Calculations
5.3. Reset
5.4. Link-Up Sequence
5.5. Error Detection, Reporting, and Recovering Mechanism
5.6. CRC-32 Error Injection
5.7. FIFO ECC Protection
5.8. User Data Interface Waveforms
5.9. Signals
5.10. Accessing Configuration and Status Registers
5.1.1. Serial Lite III Streaming Source Core
5.1.2. Serial Lite III Streaming Sink Core
5.1.3. Serial Lite III Streaming IP Core Duplex Core
5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode
5.1.5. Stratix® 10, Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations
Visible to Intel only — GUID: bhc1460601636782
Ixiasoft
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
This section describes the Serial Lite III Streaming Intel® FPGA IP clocking architecture and usage models targeting streaming applications.
The Serial Lite III Streaming Intel® FPGA IP has two clocking options to support a variety of streaming applications:
- Standard Clocking Mode (SCM):
- In this clocking mode, there is no PPM difference (mesochronous system) in both source and sink cores for Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V devices. The user interface clock and IP core clock are generated from the same clock source in both source and sink cores.
- For Stratix® 10 devices, this clocking mode is the same as advanced clocking mode for source core. For sink core, a user interface clock is required to drive the adaptation module in the core. To design a mesochronous system, Intel recommends to use the same clock source for transceiver input clock in both source and sink cores.
- Advanced Clocking Mode (ACM):
- In this clocking mode, for source core, you are required to manage any PPM difference between the user interface logic domain and the transceiver clock domain by throttling the data input or use the same clock source for user interface and transceiver clock domains. The IP does not support any PPM tolerance between the user interface domain and the transceiver clock domain. For sink core, there is no PPM differences because you are expected to use the recovered clock for user interface logic.
The following sections describe the clocking architectures for Stratix® 10, Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V GZ devices.