Serial Lite III Streaming Intel® FPGA IP User Guide

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ID 683330
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference 2. About the Serial Lite III Streaming Intel® FPGA IP 3. Getting Started 4. Serial Lite III Streaming IP Core Design Examples 5. Serial Lite III Streaming Intel® FPGA IP Functional Description 6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines 7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers 8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines 9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
2. About the Serial Lite III Streaming Intel® FPGA IP x
2.1. Serial Lite III Streaming Intel® FPGA IP Protocol 2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes 2.3. Performance and Resource Utilization
2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes x
2.2.1. Continuous Mode 2.2.2. Burst Mode
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Intel® FPGA IP Evaluation Mode 3.3. Specifying IP Core Parameters and Options 3.4. Serial Lite III Streaming Intel® FPGA IP Parameters 3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs 3.6. IP Generation Output ( Quartus® Prime Pro Edition) 3.7. IP Core Generation Output ( Quartus® Prime Standard Edition) 3.8. Simulating
3.2. Intel® FPGA IP Evaluation Mode x
3.2.1. Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying IP Core Parameters and Options x
3.3.1. Serial Lite III Streaming Intel® FPGA IP Parameter Editor 3.3.2. Arria® 10 and Cyclone® 10 GX Designs
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters x
3.4.1. Parameters 3.4.2. Parameter Settings for Stratix® 10 Devices 3.4.3. Parameter Settings for Arria® 10 and Cyclone® 10 GX Devices 3.4.4. Parameter Settings for Stratix V and Arria V GZ Devices
3.8. Simulating x
3.8.1. Simulating Intel® FPGA IP Cores 3.8.2. Simulation Parameters 3.8.3. Simulating and Verifying the Design
4. Serial Lite III Streaming IP Core Design Examples x
4.1. Serial Lite III Streaming IP Core Design Example for Stratix® 10 Devices 4.2. Serial Lite III Streaming IP Core Design Example for Arria® 10 and Cyclone® 10 GX Devices 4.3. Serial Lite III Streaming IP Design Examples for Stratix® V Devices
5. Serial Lite III Streaming Intel® FPGA IP Functional Description x
5.1. IP Architecture 5.2. Transmission Overheads and Lane Rate Calculations 5.3. Reset 5.4. Link-Up Sequence 5.5. Error Detection, Reporting, and Recovering Mechanism 5.6. CRC-32 Error Injection 5.7. FIFO ECC Protection 5.8. User Data Interface Waveforms 5.9. Signals 5.10. Accessing Configuration and Status Registers
5.1. IP Architecture x
5.1.1. Serial Lite III Streaming Source Core 5.1.2. Serial Lite III Streaming Sink Core 5.1.3. Serial Lite III Streaming IP Core Duplex Core 5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode 5.1.5. Stratix® 10, Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations
5.1.1. Serial Lite III Streaming Source Core x
5.1.1.1. Source Application Module 5.1.1.2. Source Adaptation Module 5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode 5.1.1.4. Source Clock Generator
5.1.2. Serial Lite III Streaming Sink Core x
5.1.2.1. Sink Application Module 5.1.2.2. Sink Adaptation Module 5.1.2.3. Lane Alignment Module 5.1.2.4. Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode 5.1.2.5. Sink Clock Generator
5.9. Signals x
5.9.1. Serial Lite III Streaming Intel® FPGA IP Interface Signals 5.9.2. Signals for Stratix® 10 Devices 5.9.3. Signals for Arria® 10 and Cyclone® 10 GX Devices 5.9.4. Signals for Stratix® V and Arria® V GZ Devices
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines x
6.1. Standard Clocking Mode 6.2. Advanced Clocking Mode 6.3. Standard Clocking Mode vs Advanced Clocking Mode 6.4. Clocking Implementation Guidelines 6.5. Core Latency
6.1. Standard Clocking Mode x
6.1.1. Standard Clocking Mode in Serial Lite III Streaming Intel® FPGA IP Core ( Stratix® 10 Devices) 6.1.2. Standard Clocking Mode in Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.2. Advanced Clocking Mode x
6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Stratix® 10 Devices) 6.2.2. Advanced Clocking Mode Structure For Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.4. Clocking Implementation Guidelines x
6.4.1. Choosing TX PLL Type
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers x
7.1. Register Map 7.2. Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines x
8.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging
8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging x
8.2.1. Source Core Link Debugging 8.2.2. Sink Core Link Debugging
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide

3.4.3. Parameter Settings for Arria® 10 and Cyclone® 10 GX Devices

Table 13.   IP
Parameter Value Default Description
General Design Options

Direction

Source, Sink, Duplex

Duplex

Supports source, sink, or full duplex transmissions.

Number of lanes

1–24 ( Arria® 10)

1–6 ( Cyclone® 10 GX)

2

 Specifies the number of lanes (equal to physical transceiver links) that are used to transfer the streaming data.
Transceiver reference clock frequency <Range supported by the transceiver PLLs> 644.53125 MHz Supports multiple transceiver reference clock frequencies for flexibility in the oscillator and PLL choices. This transceiver reference clock frequency must match the external PLL reference clock frequency.

Meta frame length in words

200–8191

200

Specifies the metaframe length.
Enable Transceiver Native PHY ADME On/Off Off Turn on to enable ADME and Optional Reconfiguration Logic parameters of the Transceiver Native PHY IP for Arria® 10 and Cyclone® 10 GX devices.
Enable M20K ECC support On/Off Off Turn on to use error correcting code (ECC) protection to strengthen the FIFO buffers from single-event upset (SEU) changes. Enables built-in error correcting code (ECC) support on the M20K embedded block memory for single-error correction, double-adjacent-error correction, and triple-adjacent-error detection.
User Interface
Required idle cycles between bursts 1, 2 2 Supports two values to optimize for bandwidth efficiency or maintain backward compatibility with existing Serial Lite III Streaming IP cores (legacy).
  • 1: Recommended for high bandwidth streaming. The same Burst Gap setting must be set for both source and sink IP core.
  • 2: For backward compatibility with Quartus II version 15.1 and older sink IP core.

Clocking mode

Standard clocking mode, Advanced clocking mode

Standard clocking mode

Specifies the clocking mode.

Refer to Serial Lite III Streaming Intel FPGA IP Clocking Guidelines for more information.

User input User clock frequency, Transceiver data rate User clock frequency

Select User clock frequency to specify the user clock input and allow the IP core to determine the transceiver data rate.

Select Transceiver data rate to specify the desired data rate and allow the IP core to determine the user clock frequency.

User clock frequency required

Minimum: 50 MHz

Maximum: Limited by the supported transceiver data rates

150 MHz

Specifies the desired frequency for the user clock input for the transmit (Standard Clocking Mode and Advanced Clocking Mode) and receive user interface (Standard Clocking Mode).

This frequency in turn determines the required transceiver data rate to support the calculated transmit and receive bandwidths.

User clock frequency output

Minimum: 50 MHz

Maximum: Limited by the supported transceiver data rates

150 MHz

Specifies the actual user clock frequency as produced by the fPLL or I/O PLL and is ideally the same as the required clock frequency. In certain very high precision situations where the desired user clock is provided up to higher decimal places, this value can vary slightly due to the fPLL or I/O PLL constraints. Change the required clock frequency to correct the issue if the minute variation is intolerable.

Transceiver data rate

required user clock frequency * overheads * 64

10.312499 Gbps

The effective data rate at the output of the transceivers, incorporating transmission and other overheads.

The parameter editor automatically calculates this value by adding the input data rate with transmission overheads to provide you with a selection of user clock frequency.

Aggregate user bandwidth

number of lanes * required user clock frequency * 64

18.75 Gbps

This value is derived by multiplying the number of lanes and user interface data rate.

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