Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes

ID 683308
Date 7/08/2024
Public
Document Table of Contents

Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) v2.1.0

Table 1.  v2.1.0 2024.07.08
Quartus® Prime Version Description Impact
24.2
  • Added support for Agilex™ 5 D-Series FPGAs and SoCs.1
  • Added the following support for Agilex™ 5 devices:
    • Added hardware support for the following design examples:
      • 10M/100M/1G ethernet design example.
      • 2.5G ethernet design example.
      • 10M/100M/1G/2.5G/5G/10G (USXGMII) ethernet design example.
    • Added support for VCS* MX simulator for all design examples.
    • Added support for signal tap debugging for the following design example:
      • 10M/100M/1G ethernet design example.
      • 2.5G ethernet design example.
      • 10M/100M/1G/2.5G/5G/10G (USXGMII) ethernet design example.
  • Removed VCS* simulator support.
1 Device support for Agilex™ 5 D-Series FPGAs and SoCs in the Quartus® Prime Pro Edition software version 24.2 is restricted. To enable D-Series device support in your instance of the Quartus® Prime Pro Edition software, contact your regional Altera sales representative.