Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes

ID 683308
Date 7/08/2024
Public
Document Table of Contents

Low Latency Ethernet 10G MAC IP Core v16.0

Table 20.  v16.0 May 2016
Description Impact
  • Support for 1G/2.5G/5G/10G (USXGMII) operating modes.
  • Design Examples for Low Latency 10G Ethernet MAC:
    • Added the following design examples:
      • 10G USXGMII Ethernet
      • 10GBase-R
      • 1G/2.5G Ethernet
      • 1G/2.5G Ethernet with 1588
      • 1G/2.5G/10G Ethernet
    • Added support for custom development board.
    • Enhanced reset scheme for the following design examples, where the MAC reset is decoupled from the PHY reset:
      • 10M/100M/1G/10G Ethernet
      • 10M/100M/1G/10G Ethernet with 1588
      • 1G/10G Ethernet
      • 1G/10G Ethernet with 1588
    • Added a Signal Tap file (.stp) for the following designs:
      • 10GBase-R Register Mode
      • 10M/100M/1G/10G Ethernet
      • 10M/100M/1G/10G Ethernet with 1588
      • 1G/10G Ethernet
      • 1G/10G Ethernet with 1588