Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes

ID 683308
Date 7/08/2024
Public
Document Table of Contents

Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.4

Table 4.  v22.0.4 2023.12.04
Quartus® Prime Version Description Impact
23.4 Change in the Clock Controller frequency port for 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Stratix® 10 devices. In the Clock Controller application, you must set 125MHz frequency to U5, OUT 5 and U5, OUT 8 ports instead of U5, OUT 0 and U5, OUT 8 ports.