Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1
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Added support for the Cyclone® 10 GX device family. | This device is only available in Quartus® Prime software version 17.1 onwards. |
Added support for the following operation modes for Stratix® 10 devices:
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Added a new feature—Peer-to-Peer:
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These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
You cannot turn on the Enable ECC on memory blocks parameter with the Enable time stamping parameter. | The IP core may not exhibit the expected behavior when both parameters are turned on at the same time. This is applicable in Quartus® Prime Pro Edition and Quartus® Prime Standard Edition version 17.0 and earlier. |
Design Examples for Low Latency 10G Ethernet MAC:
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In previous versions of the Low Latency Ethernet 10G MAC design example for Arria® 10 devices, the IOPLL and transceiver PLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs require additional constraints. This issue has been fixed in Quartus® Prime version 17.1. |
If you are upgrading designs that have these additional constraints from the previous versions of Quartus® Prime to version 17.1, you must revise the constraints. Refer to the KDB page for more information. |
10GBASE-R register mode is not supported in Stratix® 10 devices. | — |