Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes

ID 683308
Date 7/08/2024
Public
Document Table of Contents

Low Latency Ethernet 10G MAC IP Core v15.0

Table 22.  v15.0 May 2015
Description Impact
Added new registers:
  • Software reset register for TX and RX datapaths.
  • Transfer status registers for TX and RX datapaths.
  • VLAN and stacked VLAN detection disable.
  • Programmable IPG registers for 10G and 10M/100M/1G operating speeds.
If you do not upgrade your IP core, it does not have this new feature.