Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes

ID 683308
Date 7/08/2024
Public
Document Table of Contents

Low Latency Ethernet 10G MAC Intel® FPGA IP v18.0

Table 15.  v18.0 May 2018
Description Impact
Renamed Low Latency Ethernet 10G MAC IP core to Low Latency Ethernet 10G MAC Intel® FPGA IP core as per Intel rebranding.
Added support for the following operation modes for Stratix® 10 devices:
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII) with IEEE 1588v2 feature
Added support for the following operation mode for Arria® 10 devices:
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)

Added new parameter for LL Ethernet 10G MAC Intel® FPGA IP:
  • TX and RX datapath Reset/Default to Enable:

    Turning on this parameter disables TX and RX datapath during startup or CSR reset.

Design Examples for Low Latency 10G Ethernet MAC Intel® FPGA IP:
  • Added the following design example for Stratix® 10 devices:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet with IEEE 1588v2 feature
  • Added the following design example for Arria® 10 devices:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet
  • Added the following design example for Cyclone® 10 GX devices:
    • 10GBASE-R Ethernet