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1.1. Release Information
1.2. Device Family Support
1.3. Parameters
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface
1.6. Commands and Responses
1.7. Specifying the Command and Response FIFO Depths
1.8. Enabling Cryptographic Services
1.9. Using the Mailbox Client Intel® FPGA IP
1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples
1.11. Nios® II and Nios® V Processors HAL Driver
1.12. Mailbox Client Intel FPGA IP User Guide Archives
1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
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1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface
Offset (word) | R/W | 31 | 30:2 | 1 | 0 |
---|---|---|---|---|---|
Base address + 0 | W | Command | |||
Base address + 1 | W | Command last word (eop) | |||
Base address + 2 | R | Command FIFO empty space | |||
Base address + 3 | N/A | Reserved | |||
Base address + 4 | N/A | Reserved | |||
Base address + 5 | R | Response data | |||
Base address + 6 | R | Response FIFO fill level | EOP | SOP | |
Base address + 7 | R/W | Interrupt enable register (IER) | |||
Base address + 8 | R | Interrupt status register (ISR) | |||
Base address + 9 | R/W | Timer 1 enable | Timer 1 period | ||
Base address + 10 | R/W | Timer 2 enable | Timer 2 period |