Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.6.2. Error Code Responses

Table 14.  Error Codes
Value (Hex) Error Code Response Description
0 OK

Indicates that the command completed successfully.

A command may erroneously return the OK status if a command, such as QSPI_READ is partially successful.

1 INVALID_COMMAND Indicates that the currently loaded boot ROM cannot decode or recognize the command code.
3 UNKNOWN_COMMAND Indicates that the currently loaded firmware cannot decode the command code.
4 INVALID_COMMAND_PARAMETERS Indicates that the command is incorrectly formatted. For example, the length field setting in header is not valid.
6 COMMAND_INVALID_ON_SOURCE Indicates that the command is from a source for which it is not enabled.
8 CLIENT_ID_NO_MATCH Indicates that the Client ID cannot complete the request to close the exclusive access to quad SPI. The Client ID does not match the existing client with the current exclusive access to quad SPI.
9 INVALID_ADDRESS The address is invalid. This error indicates one of the following conditions:
  • An unaligned address
  • An address range problem
  • A read permission problem
  • An invalid chip select value, displaying value of more than 3
  • An invalid address in RSU case
  • An invalid bitmask value for GET_VOLTAGE command
  • An invalid page selection for GET_TEMPERATURE command
A AUTHENTICATION_FAIL Indicates the configuration bitstream signature authentication failure.
B TIMEOUT This error indicates time out due to the following conditions:
  • Command
  • Waiting for QSPI_READ operation to complete
  • Waiting for the requested temperature reading from one of the temperature sensors. May indicate a potential hardware error in the temperature sensor.
C HW_NOT_READY Indicates one of the following conditions:
  • The hardware is not ready. Can indicate either an initialization or configuration problem. The hardware may refer to quad SPI.
  • RSU image is not used to configure the FPGA.
  • RSU image is not used to configure the eASIC.
D HW_ERROR Indicates that the command completed unsuccessfully due to unrecoverable hardware error.
80 - 8F COMMAND_SPECIFIC_ERROR Indicates a command specific error due to an SDM command you used.
SDM Command Error Name Error code Description
GET_CHIPID EFUSE_SYSTEM_FAILURE 0x82 Indicates that the eFuse cache pointer is invalid.

QSPI_OPEN/

QSPI_CLOSE/

QSPI_SET_CS/

QSPI_READ_DEVICE_REG/

QSPI_WRITE_DEVICE_REG/

QSPI_SEND_DEVICE_OP/

QSPI_READ

QSPI_HW_ERROR 0x80 Indicates QSPI flash memory error. This error indicates one of the following conditions:
  • A QSPI flash chip select setting problem
  • A QSPI flash initialization problem
  • A QSPI flash resetting problem
  • A QSPI flash settings update problem
QSPI_ALREADY_OPEN 0x81 Indicates that the client's exclusive access to QSPI flash via QSPI_OPEN command is already open.
100 NOT_CONFIGURED Indicates that the device is not configured.
1FF ALT_SDM_MBOX_RESP_DEVICE_ BUSY Indicates that the device is busy due to following use cases:
  • RSU: Firmware is unable to transition to different version due to an internal error.
  • HPS: HPS is busy when in HPS reconfiguration process or HPS cold reset.
2FF ALT_SDM_MBOX_RESP_NO_VALID_RESP_AVAILABLE Indicates that there is no valid response available.
3FF ALT_SDM_MBOX_RESP_ERROR General Error.
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