Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers Icomplete Commad Tasactio Eo SDM Backpessue Eo
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.5.3. Timer Registers

Use time egistes to moito ad addess icomplete tasactios betwee host ad the Mailbox Cliet Itel® FPGA IP.

Icomplete Commad Tasactio Eo

Whe a host fails to sed the last commad wod to the Mailbox Cliet Itel® FPGA IP o the system stops sedig data befoe the last wod, the icomplete commad tasactio eo occus. Time 1 allows you to set a specific tasactio time peiod to complete each commad. Whe the time's timeout occus, ISR[4] is set to idicate the eo. To ecove the system, you must eset the Mailbox Cliet Itel® FPGA IP.

Table 10.  Time 1 Registe
Bit Fields Access Default Value 9 Desciptio
31 Time 1 eable R/W 0x0 Time 1 peiod eable bit. The bit is eabled oce.
  • 1: Eable time 1
  • 0: Disable time 1

If a time out occus, the time 1 egiste becomes disabled. You must eset the Mailbox Cliet Itel® FPGA IP.

To stat the time 1, you must e-eable it agai.
30:0 Time 1 peiod R/W 0x7FF_FFFF

Whe eabled, the time couts dow the specified peiod as the maximum umbe of clock cycles the system has ot eceived a valid commad.

The time 1 stats the cout dow as soo as the tasactio wites the fist data wod ito the Commad FIFO (base addess +0).

The time esets whe the Mailbox Cliet Itel® FPGA IP eceives complete commad tasactio, idicated by successfully witig the last wod ito the commad last wod egiste (base addess +1). Whe the time 1 esets itself, it etus to its default o othe defied value.

SDM Backpessue Eo

SDM typically backpessues while it pocesses commads ad seds esposes. The SDM backpessue eo occus whe SDM backpessues fo some time peiod ot allowig you to wite ay data ito the Mailbox fabic ad SDM. The time 2, by settig a specific wait time, allows you detect the log wait ad take steps to ecove you system. Whe a time's timeout occus, ISR[5] is set to idicate a eo. Note that this is a fatal eo eceived fom SDM, possibly idicatig a system eo. Resettig the Mailbox Cliet Itel® FPGA IP wo't ecove the system.
Table 11.  Time 2 Registe
Bit Fields Access Default Value 10 Desciptio
31 Time 2 eable R/W 0x0 Time 2 peiod eable bit. The bits is eabled oce.
  • 1: Eable time 2
  • 0: Disable time 2

If a time out occus, the time 2 egiste becomes disabled. You must eset the Mailbox Cliet Itel® FPGA IP.

To stat the time 2, you must e-eable it agai.
30:0 Time 2 peiod R/W 0x7FF_FFFF Whe eabled, the time couts dow the specified peiod as the maximum umbe of clock cycles the system has ot asseted eady high sigal. The SDM backpessues commads set by host to the Mailbox Cliet Itel® FPGA IP.
9 Resettig the Mailbox Cliet Itel® FPGA IP esets the time 1 egiste to the default value.
10

Resettig the Mailbox Cliet Itel® FPGA IP esets the time 2 egiste to the default value.

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